HW Auto Clock Gating for Memory Power Gating in IP Blocks
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Solution Overview
Problem
Current clock gating technologies in semiconductor systems are typically controlled by software, which is slower and less efficient than hardware control, and power gating of connected devices is also software-dependent, leading to inefficiencies in resource management.
Innovation Solution
Implementing hardware auto clock gating (HWACG) logic that controls clock gating of intellectual property blocks and includes a memory power controller to perform power gating of connected memory devices based on the operation state, enabling precise hardware-controlled clock and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If clock gating is controlled by software, then ease of operation is improved, but control speed and performance deteriorate
Solution Approach 1:
The clock management unit performs clock gating control autonomously through hardware logic circuits that automatically detect IP block operation states and generate corresponding clock gating signals, eliminating the need for software intervention and thereby achieving both ease of operation and high control speed
2Ease of operation
If power gating is controlled by software, then ease of operation is improved, but power consumption reduction efficiency deteriorates
Solution Approach 1:
The memory power controller autonomously controls power gating of the memory device by detecting clock gating signals from the HWACG logic and automatically generating power gating signals, achieving both ease of operation and efficient power consumption reduction through hardware-based automatic control
Data Source
AI summary
Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.