Auto Deep Power Down Control in Memory Devices
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Solution Overview
Problem
Current memory devices face challenges in reducing power consumption during low activity states, particularly in transitioning to ultra-deep power down modes without explicit commands, which can lead to inefficiencies and increased power usage due to the need for host device monitoring and potential unnecessary reset sequences.
Innovation Solution
Implementing an auto-deep power down (AUDPD) mode in memory devices that automatically enters the ultra-deep power down state upon completion of a write operation based on a configuration bit, allowing the host to enter a sleep state sooner and reducing supply current consumption, while ensuring the memory device can be awakened and return to a standby state efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory device enters ultra-deep power down mode automatically after write operations, then power consumption is reduced, but the host device cannot monitor the memory device status explicitly
Solution Approach 1:
The memory device autonomously determines whether to enter ultra-deep power down mode by checking the AUDPD configuration bit and monitoring write operation completion status without requiring continuous host intervention. The device serves itself by automatically transitioning to low-power state and handling its own status indication through the DQ[0] pin, eliminating the need for host polling or monitoring commands.
2Ease of operation
If the memory device remains in active or standby mode, then the host can maintain communication readiness, but power consumption increases
Solution Approach 1:
The memory device dynamically transitions between operational modes (active, standby, and ultra-deep power down) based on the AUDPD configuration bit setting and operational context. When AUDPD=1 and write operations complete, the device automatically enters ultra-deep power down mode. The device can be awakened by specific commands (RDID, RDSR, or reset sequence), providing flexible communication readiness only when needed rather than maintaining constant readiness.
3Loss of information
If the output is driven to indicate UDPD mode status, then the host can detect the mode state, but additional power is consumed during UDPD mode
Solution Approach 1:
The memory device drives the DQ[0] output pin to a logic high level only partially - specifically when the host issues a read status register command while the device is in ultra-deep power down mode. The output remains in high-impedance state during actual ultra-deep power down operation to minimize power consumption, and only activates when queried by the host, providing status information on-demand rather than continuously.
Data Source
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AI summary
Described are embodiments directed to memory devices, including non-volatile memory (NVM), such as flash memory devices, and/or resistive switching memories (e.g., conductive bridging random-access memory [CBRAM], resistive RAM [ReRAM], etc.). Particular embodiments can include structures and methods of operating flash and/or resistive switching memories that can be written (programmed/erased) between one or more resistance and/or capacitive states. A CBRAM storage element may be configured such that when a forward or reverse bias greater than a threshold voltage is applied across electrodes of the CBRAM storage element, the electrical properties (e.g., resistance) of the CBRAM storage element can change. Such embodiments are suitable to any type of memory device, including both volatile and non-volatile types/devices, and that may include resistive switching memory devices.