Auto-Determining Sampling Frequency for Single Wire Interfaces
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Solution Overview
Problem
Existing single wire transmission interfaces, such as S/PDIF, face challenges in accurately determining and locking sampling frequencies for wide range signals, requiring complex algorithm design and increased operating time.
Innovation Solution
An auto-determining sampling frequency method and device that utilizes a Phase-Locked Loop (PLL) in a clock and data recovery circuit to detect period widths of input signals, allowing for the determination of sampling frequency ranges and reducing the time needed to lock the frequency, without relying on a Micro Control Unit (MCU).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog circuit is used to acquire data supporting wide range sampling frequency, then the adaptability is improved, but the device complexity and operating time increase
Solution Approach 1:
The patent replaces the conventional analog circuit-based frequency detection mechanism with a digital logic circuit system. The sampling clock determining circuit uses digital counters and comparators to detect period widths and determine sampling frequencies, substituting complex analog algorithms with simpler digital logic operations. This maintains wide frequency range adaptability while reducing algorithmic complexity.
Solution Approach 2:
The patent introduces a sampling clock determining circuit as an intermediary component between the clock and data recovery circuit and the data processing unit. This intermediary circuit automatically determines the sampling frequency range by detecting period widths of preamble and data bits, eliminating the need for complex adaptive algorithms in the main processing path.
2Reliability
If analog circuit with clock and data recovery is used, then the data recovery capability is improved, but the locking time increases
Solution Approach 1:
The patent performs preliminary determination of the sampling frequency range before the main data recovery process begins. The sampling clock determining circuit analyzes the period widths of preamble and data bits in advance to establish the appropriate sampling frequency range, allowing the clock and data recovery circuit to lock onto the correct frequency more quickly without requiring extensive adaptive searching.
3Device complexity
If digital logic is used to determine sampling frequency, then the device complexity is reduced, but the measurement precision requirement increases
Solution Approach 1:
The patent uses the recovered clock signal as a sampling clock to acquire period widths of the input signal. By copying the timing characteristics of the recovered clock and using them to measure the input signal periods, the system achieves precise frequency determination through digital logic without requiring high-precision direct measurement circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method speeds up the determination of sampling frequencies for single wire transmission interfaces by using digital logic to detect frequency ranges, reducing the load on analog circuits and simplifying the frequency-locking process, thereby improving the efficiency of clock and data recovery.
Implementation Method 1
utilizing a sampling clock generated by a Phase-Locked Loop (PLL) in a clock and data recovery circuit
Data Source
AI summary
The present disclosure provides an auto-determining sampling frequency method. The method is for determining sampling frequency for an input signal of a single wire transmission interface. Each frame of the input signal includes a preamble and binary data presented in a plurality of bits. The method includes utilizing an internal sampling clock to acquire a plurality of period widths of the preamble and the binary data in the input signal and determining range of the sampling frequency according to the detected period widths of the preamble and the binary data.