Auto Pipeline Insertion for HDL Throughput Optimization
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Solution Overview
Problem
Existing code generation tools for high-level development environments, such as Simulink and MATLAB, do not effectively optimize hardware description language (HDL) code for increased throughput by automatically inserting pipelines and optimizing register placement, leading to suboptimal execution times and resource utilization.
Innovation Solution
A system comprising an Intermediate Representation (IR) builder, scheduler, pipeline insertion engine, and HDL code generator that automatically inserts pipeline registers into the HDL code, using a bounded scheduling algorithm to minimize overall execution time and optimize pipeline stages, while providing annotated program specifications for user design refinement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipeline registers are manually inserted in HDL code, then throughput can be optimized, but the complexity of code generation increases and manual optimization is time-consuming
Solution Approach 1:
The system enables self-service by implementing an automated pipeline insertion mechanism that analyzes the control data flow graph and autonomously determines optimal register placement locations, eliminating the need for manual intervention while achieving throughput optimization
Solution Approach 2:
The patent introduces an intermediary component (pipeline insertion engine) that acts as a mediator between the code generation tools and the HDL code, automatically analyzing the control data flow graph and inserting pipeline registers at optimal locations without requiring direct manual manipulation of the code
2Speed
If more pipeline stages are added to increase throughput, then execution time per stage decreases, but the overall device complexity and resource utilization increase
Solution Approach 1:
The system dynamically adjusts the parameter of pipeline stage depth by analyzing the control data flow graph and determining the optimal number of pipeline stages based on the specific computational requirements, rather than using a fixed or overly complex pipeline structure
Solution Approach 2:
The patent applies segmentation by dividing the computational graph into appropriate pipeline stages based on data dependencies and critical path analysis, creating a balanced segmentation that optimizes execution speed without unnecessarily increasing device complexity
3Loss of time
If automated pipeline insertion is implemented, then optimization time is reduced, but the scheduling algorithm complexity increases
Solution Approach 1:
The system performs preliminary action by pre-analyzing the control data flow graph to identify critical paths and data dependencies before pipeline insertion, allowing the scheduling algorithm to make informed decisions without requiring complex real-time optimization
Data Source
AI summary
A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.