Auto Program NAND Flash Memory Testing
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Solution Overview
Problem
Conventional NAND flash memory testing requires repetitive input of commands and external data, making the process time-consuming and cumbersome.
Innovation Solution
A method for automatically testing NAND flash memory by inputting a single 'auto program' command, generating specific data patterns internally, and repeating programming operations with increasing bias voltage, allowing for testing at page, block, or chip levels without external data input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional page-based program commands are repeatedly input for testing, then the memory can be tested thoroughly, but the test process becomes time-consuming and cumbersome
Solution Approach 1:
The patent pre-arranges test data patterns (such as all 0s, all 1s, alternating patterns) and test command sequences within the memory device before testing begins. When a test command is received, the memory internally retrieves and executes these pre-prepared test sequences without requiring external data input for each operation, thereby reducing test time while maintaining thoroughness
Solution Approach 2:
The memory device performs self-testing by internally generating and executing test commands and data patterns without external intervention. The test data is stored within the memory itself, and the memory autonomously retrieves and processes this data according to test commands, eliminating the need for external equipment to repeatedly input data and reducing overall test time
2Measurement precision
If external data is input for each test operation, then accurate test coverage is achieved, but the operation becomes complex and time-consuming
Solution Approach 1:
The memory device autonomously generates and executes test data patterns internally without requiring external equipment to prepare and input data. The device self-manages the test process by retrieving pre-stored test patterns and commands from its internal memory, significantly simplifying the operation while maintaining comprehensive test coverage
Solution Approach 2:
The test data storage structure is designed to universally accommodate multiple test patterns (all 0s, all 1s, alternating patterns, etc.) and various test operations (read, write, erase cycles). This universal design allows a single test command to trigger comprehensive testing across different data patterns and memory regions, improving both ease of operation and test coverage accuracy
3Reliability
If multiple test commands are input sequentially for erase/program cycling, then complete memory cycling is achieved, but the testing process becomes cumbersome
Solution Approach 1:
The patent pre-stores complete erase/program cycle command sequences and associated data patterns within the memory device. When a test command is received, the memory internally retrieves these pre-arranged cycle sequences and executes them automatically without requiring external equipment to repeatedly input multiple commands, thereby achieving complete cycling while simplifying operation
Solution Approach 2:
The memory device autonomously executes complete erase/program cycles by internally managing command sequences and data patterns. The device self-manages the entire cycling process including retrieving test commands, executing program operations with appropriate data patterns, and performing erase operations, all without external intervention, making the process both complete and easy to operate
Data Source
AI summary
Disclosed is a memory test method including receiving a memory test command, receiving pattern information for generating a data pattern to be written in a memory cell, and programming the memory cell according to the pattern information. According to this method, it is not required to receive external data to be programmed in a cell array.