Auto-Ranging PLL Clock Multiplier for Wide Reference Locking

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Solution Overview

Problem

Phase-locked loops (PLLs) face challenges in adapting to a wide range of input reference signals, requiring a stable circuit that can lock frequencies from a fraction of a cycle per second up to several gigahertz.

Innovation Solution

A mixed-mode electronic circuit with a PLL cell implemented in CMOS semiconductor technology, employing an auto-range algorithm and differential ring oscillator, along with threshold comparators and a finite state machine, to lock to input reference frequencies ranging from 22.5 MHz to 148.5 MHz, ensuring stability and minimizing dead zones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a PLL is designed to accept a wide range of input reference signals, then the adaptability of the circuit is improved, but the stability of the PLL is degraded

Engineering Contradiction:

Improveadaptability to input reference signalsVSAvoidstability of the PLL circuit

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent implements an auto-ranging algorithm that dynamically adjusts the PLL operating parameters based on the detected input reference frequency. The system transitions between different operating ranges (e.g., 22.5-45 MHz, 45-90 MHz, 90-148.5 MHz) by adjusting divider ratios and VCO tuning ranges, allowing the circuit to adapt to wide frequency variations while maintaining stability within each range.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes key operating parameters including the feedback divider ratio (N), input divider ratio (M), and VCO tuning range based on the detected input frequency. By switching between predetermined operating ranges with optimized parameter sets, the system achieves both wide adaptability and stable operation across different reference signal conditions.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If the PLL operates at high frequencies up to several gigahertz, then the productivity is improved, but the reliability of locking is degraded

Engineering Contradiction:

Improveoutput frequency rangeVSAvoidlocking reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent divides the wide frequency operating range into multiple discrete operating ranges (e.g., 22.5-45 MHz, 45-90 MHz, 90-148.5 MHz for reference inputs, with corresponding VCO output ranges). Each range is optimized with specific divider ratios and VCO tuning parameters to ensure reliable locking at high frequencies while maintaining overall system productivity across the full frequency spectrum.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If the PLL is designed for wide frequency range operation, then the adaptability is improved, but the device complexity is degraded

Engineering Contradiction:

Improvefrequency range coverageVSAvoidcircuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal PLL architecture that can operate across wide frequency ranges using a single integrated circuit design. The auto-ranging algorithm and reconfigurable divider networks allow the same hardware to serve multiple frequency bands and applications, achieving frequency range coverage of 22.5-148.5 MHz reference inputs with 550-1100 MHz VCO outputs without requiring multiple specialized circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7940128B2High speed PLL clock multiplier

Publication Date: 2011.05.10 SYNOPSYS INC

AI summary

The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.