Auto-Refresh Pulse Width Control for Stable DRAM Row Addressing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DRAM circuits face challenges in maintaining normal auto-refresh operations during both high-speed and low-speed operations due to excessively short or long enable periods of the auto-refresh signal, leading to issues like flag signal disappearance and simultaneous enabling of auto-refresh and counter enable signals, resulting in abnormal counter enable signals and incorrect internal row addresses.
Innovation Solution
A circuit is developed to control the pulse width of the auto-refresh signal using pulse width controllers with delay units and logic units to adjust the enable period, ensuring the auto-refresh signal has a predetermined duration, preventing overlap with the counter enable signal and maintaining consistent internal row addresses across different operation speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the enable period of the auto-refresh signal is shortened to accommodate high-speed operations, then the DRAM can operate at higher speeds, but the flag signal may disappear during the operation causing abnormal counter enable signals
Solution Approach 1:
The circuit generates the flag signal in advance before the auto-refresh operation is fully executed. By preliminarily generating the flag signal based on the auto-refresh command signal, the system ensures the flag signal is available and stable even when the enable period is shortened for high-speed operations, preventing the flag signal from disappearing during the operation.
2Reliability
If the enable period of the auto-refresh signal is extended to ensure flag signal stability, then the flag signal remains stable during high-speed operations, but the auto-refresh signal and counter enable signal may simultaneously enable during low-speed operations causing incorrect internal row addresses
Solution Approach 1:
The refresh operation is divided into distinct phases with separate control signals. The auto-refresh signal controls the refresh operation while the counter enable signal controls the internal row address generation. By segmenting the control signals and their enable periods, the system prevents simultaneous enabling of both signals during low-speed operations, ensuring accurate internal row address generation while maintaining flag signal stability.
Solution Approach 2:
Different enable periods are applied to different parts of the control signal system. The auto-refresh signal has a longer enable period to ensure flag signal stability, while the counter enable signal has a specifically controlled enable period that prevents overlap with the auto-refresh signal during low-speed operations. This local differentiation of signal characteristics resolves the contradiction between stability and precision.
3Device complexity
If a single enable period is used for the auto-refresh signal, then the circuit design is simplified, but the system cannot accommodate both high-speed and low-speed operations with different timing requirements
Solution Approach 1:
The control circuit dynamically adjusts the enable periods of different signals based on operation conditions. The auto-refresh signal and counter enable signal have different, dynamically controlled enable periods that are generated based on the auto-refresh command signal timing. This dynamic control allows the system to adapt to both high-speed and low-speed operations while maintaining proper signal timing relationships.
Data Source
AI summary
A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and generating a second refresh signal having a second refresh signal, and a second pulse width controller for receiving the second refresh signal, and generating a third refresh signal having a third enable period.