Auto-Trim Circuit for IC Configuration

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Solution Overview

Problem

The existing methods for setting trim bits in integrated circuits are time-consuming and costly, often requiring extensive testing of multiple combinations, which may not always find the optimal set of trim bits, and necessitate the creation of a new test program for each circuit design.

Innovation Solution

An auto-trim circuit that determines coarse and fine trim bits using a sample clock generator, calibration circuit, and register circuit, reducing the need for extensive testing by iteratively adjusting and storing trim bits until the desired operating point is achieved, thereby minimizing design time and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a new test program is designed for each circuit to set trim bits, then the trim bits can be accurately determined, but the design time and cost increase significantly

Engineering Contradiction:
Improvetrim bit accuracyVSAvoiddesign time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent implements a universal auto-trim circuit that can determine trim bits for multiple different circuit designs using a single standardized test program. The circuit includes a calibration circuit that works with various circuit types (DAC, ADC, PLL, etc.) without requiring custom test programs for each design, thus reducing design time while maintaining accuracy

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The auto-trim circuit enables circuits to automatically determine their own trim bits without external intervention. The calibration circuit self-calibrates by measuring circuit performance and automatically adjusting trim bits to achieve desired operating points, eliminating the need for manual test program development for each circuit

Inventive Principle:
Principle #25Self-service

2Measurement precision

If all combinations of trim bits are tested to find the optimal set, then the optimum trim bits can be found, but the process becomes very time-consuming and intensive

Engineering Contradiction:
Improveoptimum trim bit selectionVSAvoidtesting efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The calibration circuit implements a feedback mechanism where trim bits are adjusted based on measured circuit performance. The circuit measures the actual performance, compares it to the desired operating point, and uses this feedback to iteratively adjust trim bits until the optimal setting is achieved, avoiding exhaustive testing of all combinations

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies coarse trimming first to bring the circuit close to the desired operating point, then applies fine trimming to achieve precise optimization. This two-stage approach reduces the search space and computational effort compared to testing all combinations from scratch

Inventive Principle:
Principle #10Preliminary action

3Reliability

If exhaustive testing of trim bit combinations is performed, then complete coverage is achieved, but the process may not find the optimum bit set and remains time-intensive

Engineering Contradiction:
Improveparameter satisfactionVSAvoidcalibration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs coarse trimming first to satisfy basic parameter requirements and bring the circuit into the acceptable operating range. This preliminary action ensures parameter satisfaction while reducing the subsequent fine-tuning search space, achieving reliable results faster than exhaustive testing

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7853845B2Circuit and method for integrated circuit configuration
Publication Date: 2010.12.14 ATMEL CORP
  • US7853845B2 patent drawing
  • US7853845B2 patent drawing
  • US7853845B2 patent drawing

AI summary

An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits.