Four-Phase Auto-Zero Amplifier Circuit for Low Glitch Offset Correction
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Solution Overview
Problem
Prior art instrumentation amplifiers suffer from significant output voltage glitches due to clock feed-through and auto-zero stage mismatches, leading to noise and error propagation, which limits their usability in low-noise applications.
Innovation Solution
A four-phase auto-zeroing instrumentation amplifier circuit that individually calibrates each auto-zero stage to a stable reference voltage level, using a chopped voltage reference circuit with four phases (A, B, C, D) to minimize glitch voltage and capacitively coupled charge, and employs a switch to short-circuit auto-zero stage outputs to zero before signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a two-phase auto-zeroing instrumentation amplifier is used, then the circuit complexity is reduced, but significant output voltage glitches occur due to clock feed-through and auto-zero stage mismatches
Solution Approach 1:
The patent divides the auto-zeroing process into four distinct phases (A, B, C, D) instead of two, with each phase performing a specific calibration function. This segmentation allows individual calibration of each auto-zero stage to the same reference voltage level, eliminating the glitching caused by mismatched calibration levels while maintaining manageable circuit complexity through systematic phase organization.
Solution Approach 2:
The patent performs preliminary calibration of all auto-zero stages to a stable reference voltage level during phases A and C before signal transmission. By pre-calibrating the stages and using switches to short-circuit outputs to zero before signal transmission, the system eliminates glitch voltages that would otherwise occur during operation, achieving low-noise performance without excessive complexity.
2Object-generated harmful factors
If individual calibration of each auto-zero stage is implemented, then glitch voltage is minimized, but the device complexity increases
Solution Approach 1:
The patent implements periodic four-phase calibration cycles where each auto-zero stage is individually calibrated during specific phases (stage 1 during A/C, stage 2 during B/D). This periodic action allows individual calibration of each stage to the same reference voltage, minimizing glitch voltage, while the repeating cycle pattern keeps the control logic manageable and the overall device complexity controlled.
Solution Approach 2:
The patent uses switches as intermediary elements to connect each auto-zero stage output to a common zero reference level during calibration phases. These intermediary switches enable individual calibration without requiring complex direct interconnections between stages, simplifying the overall device structure while achieving the goal of minimizing glitch voltage through precise individual calibration.
3Stability of the object's composition
If a chopped voltage reference circuit is used, then reference voltage stability is improved, but capacitively coupled charge and noise are introduced
Solution Approach 1:
The patent performs preliminary short-circuiting of auto-zero stage outputs to zero using switches before signal transmission phases. This preliminary action discharges any capacitively coupled charge that may have been introduced during the calibration phases, eliminating the harmful effect while preserving the benefit of stable reference voltage from the chopped voltage reference circuit.
Solution Approach 2:
The patent acknowledges that the chopped voltage reference circuit introduces capacitively coupled charge during calibration, but converts this potential harm into a benefit by using the same charging mechanism to establish precise reference levels during phases A and C, then safely discharging the stored charge before signal transmission. The harmful capacitively coupled charge becomes useful for establishing calibration references.
Data Source
AI summary
An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin−) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).