Auto-Zero Buffer Circuit for Display Offset Correction

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Solution Overview

Problem

Existing electronic display technologies face inefficiencies and inaccuracies in removing offsets in display circuitry, particularly due to high power consumption and memory usage in factory calibration processes, and the ineffectiveness of chopping techniques at lower refresh rates, which can lead to kickbacks and disturbances in pixel data.

Innovation Solution

An auto-zero circuit topology is employed during the vertical blanking interval, where capacitors are used to store correction voltages and absorb error currents, minimizing leakage current and preserving offset corrections over time, thereby reducing power consumption and improving accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If factory calibration process is employed to remove offsets, then offset correction is achieved, but manufacturing time and cost increase

Engineering Contradiction:
Improveoffset correction accuracyVSAvoidmanufacturing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs offset calibration during the factory calibration process and stores the results in memory, so that the offset correction is already prepared before the display device is used. This preliminary action eliminates the need for continuous offset correction during operation, reducing both manufacturing time and operational power consumption.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the offset correction data and stores it in memory, allowing the system to use stored correction values instead of continuously performing calibration measurements. This copying approach significantly reduces the time and computational resources needed during operation.

Inventive Principle:
Principle #26Copying

2Measurement precision

If factory calibration process is employed to remove offsets, then offset correction is achieved, but memory space is consumed

Engineering Contradiction:
Improveoffset correction accuracyVSAvoidmemory space
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent uses volatile memory to store offset calibration data, which is inexpensive and requires minimal space. The calibration data is refreshed periodically or as needed, rather than permanently storing large amounts of correction data. This approach minimizes memory space consumption while maintaining correction accuracy.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Measurement precision

If chopping circuitry is used to remove offsets, then temporal offset removal is achieved, but kickbacks and disturbances occur at lower refresh rates

Engineering Contradiction:
Improveoffset removalVSAvoidsignal stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements periodic auto-zero assertions that operate independently of the refresh rate. Instead of using chopping circuitry that synchronizes with the display refresh, the system performs offset correction at periodic intervals that are optimized for the specific display technology, eliminating kickbacks and disturbances.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent uses feedback mechanisms to monitor and adjust offset corrections dynamically. The system continuously monitors the display output and adjusts the auto-zero timing and magnitude to maintain accuracy without causing signal disturbances, adapting to different operating conditions.

Inventive Principle:
Principle #23Feedback

4Measurement precision

If frequent auto-zero assertion is performed, then offset accuracy is maintained, but power consumption increases

Engineering Contradiction:
Improveoffset accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic auto-zero timing that adapts to the display's operational state. The system performs auto-zero corrections at optimized intervals based on the display technology type (e.g., OLED vs. LCD) and operating conditions, rather than using fixed frequent assertions. This dynamic approach maintains offset accuracy while minimizing power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the timing parameters of auto-zero assertions based on the display refresh rate and technology type. For high refresh rate displays, fewer auto-zero assertions are needed, while lower refresh rate displays receive appropriately timed corrections. This parameter optimization reduces unnecessary power consumption while maintaining accuracy.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the accuracy and efficiency of image data depiction on electronic displays by minimizing offset errors and reducing power usage, while maintaining correction properties for a longer operational period.

Implementation Method 1

capacitors are used to store correction voltages and absorb error currents, minimizing leakage current and preserving offset corrections over time

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11176888B2Auto-zero applied buffer for display circuitry
Publication Date: 2021.11.16 APPLE INC
  • US11176888B2 patent drawing
  • US11176888B2 patent drawing
  • US11176888B2 patent drawing

AI summary

A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.