Auto-Zero Circuitry for CMOS Image Sensor Fixed Pattern Noise Reduction
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Solution Overview
Problem
CMOS image sensors suffer from significant fixed pattern noise (FPN) in the readout circuitry, exceeding acceptable levels due to mismatches and offsets, which complicates noise reduction techniques like correlated double sampling.
Innovation Solution
Incorporating an auto-zero circuitry that clamps the output voltage of each pixel to a stable reference, preventing the generation of FPN by isolating dc offsets and noise in the programmable gain amplifier (PGA), thereby reducing FPN to acceptable levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If correlated double sampling (CDS) is used to reduce FPN, then FPN reduction is achieved, but the system complexity increases significantly
Solution Approach 1:
The patent extracts and removes the offset voltage component from the signal path using a dedicated offset storage node (second node) that is separate from the signal storage node (first node). By isolating the offset voltage in a separate node and subtracting it from the original signal, the system reduces FPN without requiring the complex CDS architecture, thus lowering system complexity while maintaining noise reduction effectiveness
Solution Approach 2:
The patent segments the sampling process into distinct stages: offset sampling phase and signal sampling phase. During the offset sampling phase, only the offset voltage is captured and stored in the second node. During the signal sampling phase, the actual signal plus offset is captured in the first node. This segmentation allows for simpler, more modular circuit implementation compared to traditional CDS, reducing overall system complexity
2Productivity
If readout circuitry operates at higher speed, then image processing speed increases, but FPN increases beyond acceptable levels
Solution Approach 1:
The patent performs preliminary offset characterization by sampling and storing the offset voltage in the second node before the actual signal is processed. This preliminary action of capturing the offset component separately allows the readout circuitry to operate at higher speeds during signal acquisition without being constrained by FPN, as the offset has already been isolated and can be subtracted later, thus enabling high-speed operation while maintaining low FPN
Solution Approach 2:
The patent introduces an intermediary offset storage node (second node) that mediates between the high-speed signal path and the offset correction mechanism. This intermediary node captures and holds the offset voltage, allowing the main signal path to operate at high speed without being degraded by FPN, thus resolving the contradiction between speed and noise performance
3Power
If PGA amplifies the data, then signal strength increases, but dc offset and noise are generated
Solution Approach 1:
The patent extracts the dc offset component from the amplified signal path by using the second node to store and represent the offset voltage. This extracted offset can then be subtracted from the amplified signal, removing the harmful dc offset and associated noise that would otherwise be present, thus allowing the PGA to provide strong signal amplification while maintaining clean output by eliminating the offset component
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The auto-zero circuitry effectively reduces FPN from 2.41% to 0.59%, maintaining image quality and allowing for increased image processing speed without significant noise increase, as demonstrated by test results.
Implementation Method 1
A photodiode is for generating data according to received light
Implementation Method 2
The auto-zero circuitry is coupled to the PGA for eliminating a dc offset and noise of the PGA
Data Source
AI summary
Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.