High-Gain Auto-Zero Comparator Circuit for Offset Cancellation
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Solution Overview
Problem
Electronic circuits, especially comparators in SAR ADCs, face challenges in eliminating offset voltage due to mismatches between differential input pairs and current mirrors, which vary with temperature, supply voltage, and process corners, leading to differential non-linearity errors.
Innovation Solution
A high gain auto-zeroing system that includes a pair of source followers, capacitors for sampling offset voltage, and diode-connected transistors to generate biasing voltage signals, which modulate the control terminals of the source followers to eliminate offset voltage through a feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard auto-calibration technique is used to achieve low offset voltage, then offset voltage is reduced, but device complexity and cost increase
Solution Approach 1:
The patent extracts the offset voltage from the signal path by using a dedicated auto-zero circuit that samples and stores the offset separately. The offset is captured during a calibration phase and then subtracted from subsequent measurements, removing the need for complex system-level calibration while maintaining low offset performance
Solution Approach 2:
The patent introduces an intermediary auto-zero circuit that acts as a mediator between the differential input pair and the rest of the system. This circuit captures the offset through sampling capacitors and uses it to generate compensation signals, simplifying the overall system architecture while achieving precise offset cancellation
2Speed
If minimum device lengths are used in comparators for faster operation, then speed is improved, but mismatch between differential input pairs and current mirrors increases
Solution Approach 1:
The patent applies preliminary action by measuring and storing the offset voltage in advance during a calibration phase. The offset is captured before the actual comparison operation using sampling capacitors, and this pre-measured offset is then used to compensate for mismatches during fast operation, allowing minimum device lengths to be used without sacrificing precision
Solution Approach 2:
The patent implements feedback by using the sampled offset voltage to generate compensation signals that are fed back to the differential input stage. The auto-zero circuit continuously monitors and corrects for mismatches between the differential pair and current mirrors, maintaining high precision even with minimum-length devices optimized for speed
3Manufacturing precision
If offset trimming is performed to correct mismatches, then manufacturing precision is improved, but device complexity and time-to-market increase
Solution Approach 1:
The patent applies self-service by enabling the circuit to automatically measure and correct its own offset without external intervention. The auto-zero circuit autonomously samples the offset during calibration and generates compensation signals during operation, eliminating the need for manual trimming processes and reducing time-to-market while maintaining high precision
Data Source
AI summary
A method and system for high gain auto-zeroing arrangement for electronic circuits. An auto-zero electronic circuit eliminates an offset associated with a test electronic circuit. The test electronic circuit includes a pair of input terminals configured to receive an input voltage signal and a pair of output terminals. The auto-zero electronic circuit includes a pair of source followers, and a pair of capacitors coupled to the output terminals of the test electronic circuit for sampling the offset associated with the test electronic circuit. The auto-zero electronic circuit also includes a differential pair coupled to the pair of source followers. A pair of diode-connected transistors, coupled to the differential pair, is configured to generate biasing voltage signals. The biasing voltage signals modulate the control terminals of a pair of input source followers of the test electronic circuit and eliminate the offset associated with the test electronic circuit.