Auto-Zero Comparator Circuit for Image Sensor Reset Noise
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Solution Overview
Problem
Existing CMOS image sensors face challenges in achieving high-performance analog-digital conversion due to reset noise in pixels, which affects image quality.
Innovation Solution
A comparator and image sensor design that includes a pixel array with a ramp generator and analog-digital conversion circuit, utilizing a comparator with adjustable auto-zero levels and transistors configured to manage parasitic capacitance, enhancing the bandwidth and efficiency of signal conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional comparator design is used in the analog-digital conversion circuit, then the circuit structure is simple, but reset noise cannot be effectively reduced and image quality deteriorates
Solution Approach 1:
The comparator is divided into multiple functional blocks: a first comparator for initial comparison, a second comparator for refined comparison, and an auto-zero circuit for noise cancellation. This segmentation allows each block to perform a specific function, effectively reducing reset noise while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The auto-zero circuit performs preliminary action by pre-compensating for offset voltages and reset noise before the main comparison operation. By adjusting the auto-zero level in advance, the circuit eliminates harmful factors before they affect the final conversion, improving image quality without requiring complex real-time correction mechanisms.
2Measurement precision
If the auto-zero level is adjusted to reduce reset noise, then image quality improves, but the circuit requires additional control mechanisms increasing complexity
Solution Approach 1:
The auto-zero adjustment mechanism is merged with the comparator structure itself, sharing transistors and circuit elements between the comparison and auto-zero functions. This integration allows precise signal conversion while avoiding the need for separate, complex control mechanisms, as the same hardware performs both comparison and noise cancellation.
Solution Approach 2:
The comparator circuit is designed with multi-functionality, where the same transistors and circuit blocks serve dual purposes: performing the main comparison operation and executing auto-zero adjustment. This universality reduces the need for additional dedicated control mechanisms, maintaining signal precision while limiting complexity growth.
3Productivity
If transistors are configured to manage parasitic capacitance, then bandwidth and conversion efficiency improve, but the device complexity increases
Solution Approach 1:
The transistor configuration employs dynamic switching to manage parasitic capacitance, where transistors are selectively activated and deactivated based on the conversion stage. This dynamic approach optimizes bandwidth and conversion efficiency by minimizing capacitive effects during critical comparison periods, while the structured switching pattern keeps the control logic manageable rather than overly complex.
Solution Approach 2:
The transistor configuration changes operational parameters such as gate voltage and switching timing to manage parasitic capacitance effects. By dynamically adjusting these parameters during different conversion phases, the circuit achieves high conversion efficiency without requiring a permanently complex transistor architecture, as the complexity is temporarily activated only when needed.
Data Source
AI summary
Provided are a comparator and an image sensor including the same. The comparator includes a first input transistor including a gate connected to a first input node, a second input transistor including a gate connected to a second input node, a first load transistor including a drain connected to the first input transistor, a second load transistor including a drain connected to the second input transistor, a first shift transistor including a drain connected to the first load transistor, a second shift transistor including a drain connected to the second load transistor, a first bottom switch connected to the first load transistor in parallel, a second bottom switch connected to the second load transistor in parallel, a first top switch connected to the first shift transistor in parallel, and a second top switch connected to the second shift transistor in parallel.