High-Frequency Comparator With Auto-Zero Latch for SHA-Less ADCs
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Solution Overview
Problem
Conventional comparators used in analog-to-digital converters face challenges with input-frequency-dependent and statistical offsets, leading to variations in trip point and group delay, particularly at high frequencies, which affect response time and accuracy.
Innovation Solution
The design incorporates a pre-amplifier stage, an isolation switch stage, and a latch core with cross-coupled inverters and impedances to auto-zero the statistical offset and reduce group delay, enabling a low-offset, high-frequency signal comparator suitable for SHA-less ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dedicated front-end SHA is used, then timing requirements at high input frequencies are improved, but power consumption increases, noise increases, and chip area increases
Solution Approach 1:
The patent removes the dedicated front-end SHA from the ADC architecture, extracting this function to reduce power consumption and chip area. Instead, the comparator is designed to directly handle high-frequency input signals without requiring a separate sampling and hold stage, thereby eliminating the power and area overhead while maintaining timing performance.
Solution Approach 2:
The comparator is designed to perform multiple functions: it directly samples, holds, and compares high-frequency input signals without requiring a dedicated front-end SHA. This multi-functional design allows the same circuit to handle both the sampling/holding operations and the comparison operation, reducing overall system complexity and power consumption.
2Stability of the object's composition
If isolation switches are introduced to compensate for input-frequency dependency, then trip point stability is improved, but statistical offset increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the latch inputs to a fixed voltage level before the comparison operation begins. This preliminary charging ensures that the latch starts from a known, stable state, which compensates for input-frequency dependency without requiring isolation switches that would introduce statistical offset. The pre-charge phase prepares the circuit in advance to maintain trip point stability.
3Measurement precision
If device sizes are optimized to reduce statistical offset, then measurement precision is improved, but other design specifications may be compromised
Solution Approach 1:
The patent changes the operating parameters of the comparator, specifically using a differential input structure and optimizing the bias currents and transistor aspect ratios to achieve low statistical offset without requiring extreme device size optimizations. By adjusting these parameters, the design maintains measurement precision while preserving flexibility to meet other design specifications such as power consumption and speed requirements.
Data Source
AI summary
A high frequency input signal comparator for optimizing group delay, reducing input frequency dependent offset and an offset auto-zeroing latch core are described. The comparator may include an isolation switch stage, and a latch core. The isolation switch stage may isolate latch core depending upon a control signal, thereby reducing input frequency dependent offset. The latch core may include a pair of inverters cross coupled via an impedance to one another. The latch core may include latch switches selected to attain a certain gain across the individual inverters comprising the latch core while resetting the latch core. The gain across the individual inverters during the acquire/reset phase may bootstrap the coupling impedances, thereby reducing loading and group delay at the input of the latch core. The coupling impedances may be designed to minimize or auto-zero statistical offset, thereby minimize input referred offset.