Automata Processor Hardware for Pattern Mining Speed
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Solution Overview
Problem
Current pattern mining techniques, such as sequential pattern mining (SPM) and disjunctive rule mining (DRM), face performance challenges due to their inability to efficiently handle large datasets and complex hierarchical patterns, with existing algorithms like GSP, SPADE, and PrefixSpan struggling with scalability and speed on multicore and GPU architectures.
Innovation Solution
The implementation of a hardware-accelerated framework using the Automata Processor (AP) for SPM and DRM, employing automaton design strategies like linear design and reduction design to leverage parallelism, significantly improving performance by flattening hierarchical patterns into strings and utilizing bitwise parallelism for matching and counting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional pattern mining algorithms (GSP, SPADE, PrefixSpan) are used on multicore CPUs or GPUs, then they can handle basic pattern mining tasks, but they struggle with scalability and speed when dealing with large datasets and complex hierarchical patterns
Solution Approach 1:
The patent replaces traditional software-based pattern mining algorithms with a hardware-based Automata Processor system. The AP uses finite automaton theory to create dedicated hardware circuits that can process sequential patterns and disjunctive rules in parallel, substituting the mechanical software execution model with a hardware-based state machine model that achieves orders of magnitude speedup.
Solution Approach 2:
The patent segments the pattern mining problem into distinct automaton components: state transition elements for pattern matching, counter elements for frequency counting, and separate processing paths for different pattern types (sequential patterns, disjunctive rules). This segmentation allows each component to be optimized independently and processed in parallel on the hardware architecture.
2Productivity
If hardware acceleration is applied to frequent set mining and string matching, then throughput and energy efficiency improve, but no hardware-accelerated solution exists for sequential pattern mining and disjunctive rule mining
Solution Approach 1:
The patent creates a universal hardware framework based on finite automata that can handle multiple pattern mining tasks including sequential pattern mining, disjunctive rule mining, frequent set mining, and string matching. The same AP hardware infrastructure with state transition elements and counter elements serves all these different algorithms, providing both high throughput and broad adaptability.
3Measurement precision
If the number of patterns to be considered increases to capture permutations among frequent itemsets, then mining accuracy improves, but computational cost increases dramatically
Solution Approach 1:
The patent performs preliminary action by pre-processing the data to identify frequent itemsets before the main pattern mining phase. The Apriori algorithm is executed first to generate candidate frequent itemsets, which then serve as the foundation for subsequent sequential pattern and disjunctive rule mining. This preliminary filtering reduces the search space and avoids considering permutations of infrequent itemsets, saving computational time while maintaining accuracy.
Solution Approach 2:
The patent introduces counter elements as intermediary components between the state transition elements and the output. These counters accumulate pattern frequencies during the automaton processing, serving as a mediator that aggregates results from multiple parallel processing paths. This intermediary mechanism enables accurate pattern identification without requiring exhaustive enumeration of all possible permutations.
Data Source
AI summary
The present invention introduces the development of a flexible CPU-AP (Computer Processing Unit-Automata Processor) computing infrastructure for mining hierarchical patterns based on Apriori algorithm. A novel automaton design strategy, called linear design, is described to generate automata for matching and counting hierarchical patterns and apply it on SPM (Sequential Pattern Mining). In addition, another novel automaton design strategy, called reduction design, is described for the disjunctive rule matching (DRM) and counting. The present invention shows performance improvement of AP SPM and DRM solutions and broader capability over multicore and GPU (Graphics Processing Unit) implementations of GSP SPM, and shows that AP SPM and DRM solutions outperform state-of-the-art SPM algorithms SPADE and PrefixSpan (especially for larger datasets).