Automata Processor NFA Acceleration for Sequential Pattern Mining
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Solution Overview
Problem
Existing sequential pattern mining (SPM) techniques face performance challenges due to the large permutation space and complex hierarchical patterns, with existing hardware accelerators like GPUs not effectively addressing true SPM needs, and existing software algorithms like SPADE and PrefixSpan struggling with large datasets.
Innovation Solution
A CPU-AP computing solution using Micron's Automata Processor (AP) to accelerate SPM by mapping sequential patterns to NFAs, flattening hierarchical patterns to strings, and employing a multiple-entry NFA strategy to maximize parallelism, reducing automaton design space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware accelerators like GPUs are used for SPM, then computational speed is improved, but the complexity of the system increases and true SPM needs are not effectively addressed
Solution Approach 1:
The patent introduces a specialized NFA automaton as an intermediary component between the input data and the pattern matching process. This automaton serves as a mediator that efficiently handles the complex hierarchical pattern matching tasks, enabling true SPM on hardware accelerators while managing system complexity through a focused, purpose-built component rather than a general-purpose solution.
Solution Approach 2:
The patent replaces conventional software-based pattern matching mechanisms with a hardware-accelerated NFA automaton implementation. By substituting the mechanical/software processing approach with a dedicated hardware automaton, the system achieves significantly improved computational speed for SPM while the automaton's structured design helps manage overall system complexity.
2Measurement precision
If existing software algorithms like SPADE and PrefixSpan are used, then pattern mining accuracy is improved, but performance on large datasets deteriorates
Solution Approach 1:
The patent fundamentally changes the processing parameters by transitioning from sequential software processing to parallel hardware processing. The NFA automaton is designed to process multiple patterns simultaneously, changing the temporal and computational parameters to achieve both high accuracy on complex hierarchical patterns and improved productivity on large datasets.
Solution Approach 2:
The patent adds a hardware acceleration dimension to the existing software algorithms. By implementing the NFA automaton on hardware accelerators, the system operates in a new computational dimension that enables simultaneous maintenance of pattern mining accuracy and improvement of processing speed on large datasets, effectively resolving the scalability limitation of conventional software approaches.
3Reliability
If the permutation space and hierarchical patterns are fully explored, then pattern mining completeness is improved, but computational cost increases dramatically
Solution Approach 1:
The patent applies preliminary action by pre-processing and organizing the pattern space into a structured NFA automaton before the main computational task. The automaton is constructed in advance with all necessary transitions and states, allowing the actual pattern matching to proceed efficiently without needing to explore the entire permutation space exhaustively, thus maintaining completeness while reducing computational cost.
Solution Approach 2:
The patent uses copying by replicating the NFA automaton structure across multiple hardware units or threads. Instead of exploring each permutation individually, the system creates multiple copies of the automaton that can process different patterns in parallel, maintaining comprehensive pattern mining coverage while significantly reducing the computational cost through parallelization.
Data Source
AI summary
A hardware accelerated solution of the SPM (Sequential Pattern Mining) is proposed using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs) The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. The multi puss pruning strategy of the GSP is implemented is the APs fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90× and 29× speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU (Central Processing Unit) and GPU (Graphics Processing Unit) GSP implementations, respectively. The proposed CPU-AP solution also outperforms the state-of-the-art PrefixSpan and SPADE (Sequential PAttern Discovery using Equivalence classes algorithms on multicore CPU by up to 452× and 49× speedups.