Automated 3D Device Structure Synthesis from Circuit Layouts
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Solution Overview
Problem
Traditional TCAD methodologies are limited by manual and time-intensive processes for generating structure files for 3D device simulations, leading to errors, inefficiencies, and difficulties in iterative design modifications due to the complexity of capturing accurate three-dimensional features and process assumptions.
Innovation Solution
An automated full structure generator program that annotates design layouts to identify functional components, generates FEOL and BEOL structure files, and merges finite element meshes, allowing for rapid and consistent creation of structure files independent of process assumptions and manual coding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual structure file generation is used, then device simulation can be performed, but the process is time-consuming and error-prone
Solution Approach 1:
The patent uses process simulation to generate a reference structure file that is copied and reused across multiple layouts. Instead of manually creating structure files for each layout, the system performs process simulation once to create a master structure file, then copies it for different device instances, significantly reducing time while maintaining accuracy through automated parameterization
Solution Approach 2:
The system enables self-service by automatically generating structure files through process simulation without requiring manual intervention. The automated program reads layout files, performs process simulation, and generates structure files independently, eliminating the need for manual coding and reducing errors associated with human operation
2Manufacturing precision
If process simulation is performed for each device instance, then accurate structure files are obtained, but computational cost and time increase significantly
Solution Approach 1:
The patent implements universality by creating a single process simulation model that can serve multiple device instances and layout configurations. The process simulation is designed to be layout-agnostic, allowing the same simulation engine to generate structure files for different device types and geometries by simply changing input parameters, thereby increasing productivity without sacrificing accuracy
Solution Approach 2:
The system uses parameter changes to adapt a single process simulation model to different device instances. By modifying geometric parameters, material properties, and process conditions in the simulation input, the same process simulation framework can accurately generate structure files for various device configurations, eliminating the need for separate simulations for each instance
3Adaptability or versatility
If manual coding is used to create structure files, then flexibility in modifying process assumptions is possible, but the process becomes labor-intensive and inconsistent
Solution Approach 1:
The patent implements dynamics by making the structure file generation process adaptive and configurable. The automated program allows users to dynamically adjust process assumptions, material parameters, and simulation conditions through input files without requiring manual recoding. This enables flexible modification of process assumptions while maintaining ease of use through automated parameterization and consistent processing
4Reliability
If iterative modification of layouts with simulation feedback is performed manually, then design optimization is achieved, but the process becomes impractical due to time constraints
Solution Approach 1:
The patent enables continuity of useful action by automating the entire structure file generation process, allowing iterative design cycles to proceed without manual intervention between iterations. The automated program can continuously generate structure files for modified layouts and feed results back to the design process, maintaining uninterrupted optimization cycles that significantly reduce the time required for design refinement while preserving design quality
Data Source
AI summary
A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.