Automated Power Domain Assignment for Network-on-Chip Elements
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Solution Overview
Problem
Existing System-on-Chip (SoC) and Network-on-Chip (NoC) architectures face inefficiencies due to manual assignment of power and voltage domains, leading to sub-optimal static power consumption and hardware area usage, especially in complex multi-core systems with varying traffic profiles and connectivity requirements.
Innovation Solution
An automated method for assigning power domains and voltage domains to NoC elements based on NoC specifications, traffic profiles, connectivity, and power constraints, using a system that identifies required elements, computes possible assignments, and optimizes using simulated annealing to minimize static power consumption and hardware area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If manual assignment of power and voltage domains is used in NoC architectures, then design flexibility is maintained, but static power consumption and hardware area are sub-optimal
Solution Approach 1:
The system performs self-service by automatically assigning power and voltage domains to NoC elements based on traffic profiles and connectivity requirements. The automated assignment mechanism eliminates manual intervention, allowing the system to optimize its own power and area characteristics through algorithmic determination of domain assignments.
Solution Approach 2:
The invention changes the parameter of domain assignment from manual to automated by introducing optimization algorithms that evaluate multiple parameters including traffic profiles, connectivity requirements, and power constraints. This parameter transformation enables systematic optimization of power consumption and hardware area through computational methods.
2Use of energy by moving object
If automated optimization is applied to reduce static power consumption, then energy efficiency improves, but computational complexity increases
Solution Approach 1:
The system performs preliminary action by conducting automated power and voltage domain assignment during the design phase before actual NoC operation. This advance optimization allows energy efficiency improvements to be baked into the architecture without adding runtime computational overhead, resolving the contradiction between optimization benefits and computational complexity.
3Area of stationary object
If hardware area is minimized through automated domain assignment, then area efficiency improves, but design flexibility decreases
Solution Approach 1:
The invention introduces dynamics by making the domain assignment adaptable to different traffic profiles and connectivity scenarios. The automated system can dynamically adjust domain assignments based on input parameters, maintaining design flexibility while achieving area optimization through systematic evaluation of multiple configuration possibilities.
4Ease of manufacture
If manual domain assignment is used, then design control is maintained, but optimization of power and area tradeoffs is insufficient
Solution Approach 1:
The system implements feedback by using optimization algorithms that evaluate the impact of domain assignments on both power consumption and hardware area. The automated mechanism provides feedback on the tradeoffs between these parameters, enabling designers to make informed decisions while maintaining control over the optimization process through configurable constraints and objectives.
Data Source
AI summary
The present disclosure relates system and method for automatic assignment of power domain and voltage domain to one or more SoC and/or NoC elements based on one or a combination of NoC and/or SoC specification/design, traffic specification, connectivity between SoC hosts that the NoC element in context is a part of, power specification (power domain and voltage domain of each host) of the hosts/SoC, and power profile(s) applicable for the NoC element in context. In another example implementation, power domain and voltage domain can be assigned to each SoC and/or NoC element based on pre-defined constraints and with an objective of reducing/minimizing static power consumption, reducing/minimizing hardware area, or identifying a tradeoff between the two parameters.