Automated Reconfigurable Processor Mapping with a Customized C Interpreter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current reconfigurable processors face challenges in automatic mapping of cryptographic algorithms due to high personnel requirements, long development cycles, inconsistent mapping results, and poor tolerance for hardware changes, making manual mapping the primary choice, which is time-consuming and error-prone.
Innovation Solution
An interpreter for reconfigurable cryptographic algorithms based on customized high-level C language, comprising an input program, compiler optimization module, data flow graph generation, and array configuration code module, automates the mapping process by using operators like BFU, SBOX, and BENES, supporting two-level loop nesting and optimizing hardware code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual mapping is used for cryptographic algorithms on reconfigurable processors, then mapping flexibility and customization are improved, but mapping time and error rate increase significantly
Solution Approach 1:
The patent introduces an intermediate representation (IR) as a mediator between the high-level cryptographic algorithm description and the low-level reconfigurable processor mapping. This IR serves as a standardized intermediate format that captures the essential computational structure of cryptographic algorithms (such as Data Flow Graphs) while being independent of specific hardware details. The compiler uses this intermediate representation to systematically transform algorithms into processor-specific configurations, eliminating the need for manual mapping while preserving adaptability through the standardized IR format.
Solution Approach 2:
The patent replaces the manual mechanical process of mapping with an automated compilation system. The compiler automatically performs the transformation from high-level algorithm descriptions to processor configurations using systematic rules and algorithms. This substitution eliminates human intervention in the mapping process, dramatically reducing mapping time and error rates while maintaining the ability to handle various cryptographic algorithms through the intermediate representation.
2Device complexity
If traditional compilation technology is used for serial processors, then compilation simplicity is improved, but parallel reconfigurable processor mapping capability deteriorates
Solution Approach 1:
The patent implements a dynamic compilation approach that adapts to the specific characteristics of parallel reconfigurable processors. The compilation system dynamically analyzes the intermediate representation of cryptographic algorithms and generates optimized mappings based on the target processor's architecture, resource availability, and performance requirements. This dynamic adaptation allows the same compilation framework to handle both simple and complex parallel mapping scenarios, bridging the gap between compilation simplicity and parallel mapping capability.
Solution Approach 2:
The patent segments the compilation process into distinct modular stages: front-end parsing, intermediate representation generation, optimization, and back-end code generation. Each stage handles specific aspects of the compilation task independently, allowing the system to manage the complexity of parallel processor mapping while maintaining overall compilation simplicity. The intermediate representation serves as a clear boundary between the simple front-end and the complex back-end mapping operations.
3Productivity
If automatic mapping tools are developed for reconfigurable processors, then mapping speed and consistency are improved, but tool maturity and availability worsen
Solution Approach 1:
The patent designs a universal compilation framework that can handle multiple cryptographic algorithms through a common intermediate representation. This multi-functional approach allows the tool to map various algorithms (such as AES, DES, RSA) using the same core compilation infrastructure, improving tool maturity through reuse and standardization while maintaining high mapping speed. The universal IR format serves as a platform that supports diverse algorithms without requiring separate specialized tools for each algorithm type.
Data Source
AI summary
The present disclosure provides an interpreter of a reconfigurable cryptographic algorithm based on customized high-level C language, in the field of information security. The interpreter includes an input program of cryptographic algorithm customized language, a compilation optimization module, an intermediate file and data flow graph generation module, a mapping module and an array generation configuration code module. The disclosure provides an automatic mapping tool for the reconfigurable processor, which can take customized high-level C language as input, and the interpreter arranges and connects computing units like operators according to the input high-level C program, to complete the mapping of the whole computing function. This can shorten the development cycle of the reconfigurable system, reduce the hardware mastery requirements for users, map the computing units of different parts to the reconfigurable processor in a more optimized way, and effectively enhance the performance of the reconfigurable processor.