Automated SoC Synthesis for Secure IP Management
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Solution Overview
Problem
The design of complex Systems on Chip (SoCs) faces challenges in minimizing time and effort due to the need for optimizing processor core specifications to accommodate expected performance levels for computer code, while existing synthesis processes are inefficient and lack secure management of trade secrets.
Innovation Solution
An automated method for managing SoC design and configuration, involving a menu-driven computer program that integrates hardware and software components, generates a merged HDL file, and allows remote interaction for design, simulation, and synthesis, ensuring secure management of proprietary IP by maintaining design processes within a secure environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual design and configuration processes are used for SoC, then designers can customize processor cores, but the time and effort required for design and manufacturing increases significantly
Solution Approach 1:
The patent pre-configures processor cores with standardized instruction sets and architectural features before integration into SoC designs. By preparing customized processor configurations in advance through automated synthesis tools, the system eliminates time-consuming manual customization steps while maintaining the ability to adapt processor specifications to different application requirements
Solution Approach 2:
The patent employs automated synthesis tools that systematically vary processor configuration parameters (such as pipeline depth, cache size, and instruction set extensions) to generate optimized processor designs. This automated parameter exploration and selection process replaces manual trial-and-error customization, significantly reducing design time while achieving optimal processor performance for specific applications
2Adaptability or versatility
If traditional synthesis processes are used, then design flexibility is maintained, but the efficiency and productivity of the design process decreases
Solution Approach 1:
The patent implements automated synthesis tools that autonomously perform processor configuration, optimization, and verification without requiring continuous human intervention. The system automatically analyzes design requirements, selects appropriate processor configurations, and generates synthesized processor designs, enabling the design process to service itself and dramatically improving productivity while preserving design flexibility through automated exploration of configuration options
Solution Approach 2:
The patent replaces manual mechanical design processes with automated electronic synthesis tools. Instead of designers manually configuring processor parameters and iterating through design options, computer-based synthesis algorithms automatically perform these tasks, substituting human manual operations with automated computational processes that are both faster and more efficient while maintaining design flexibility
3Adaptability or versatility
If proprietary IP blocks are shared with designers, then design capabilities are enhanced, but trade secret protection becomes compromised
Solution Approach 1:
The patent introduces automated synthesis tools as an intermediary layer between proprietary IP blocks and end-user designs. The synthesis tools receive high-level design specifications from users, automatically configure processor cores using proprietary IP components, and generate synthesized designs without exposing the underlying proprietary IP code to users. This intermediary process enables design capability enhancement through access to sophisticated processor configurations while maintaining trade secret protection by never directly sharing proprietary IP blocks with end users
Data Source
AI summary
A system and method for facilitating the design process of an integrated circuits (IC) is described. The system and method utilizes a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the IC. Synthesizable RTL is securely maintained on a server in a data center while providing designers graphical access to customizable IP block by way of a network portal.