Automated Test Bench Generation for Circuit Verification
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Solution Overview
Problem
The existing circuit verification processes for sub-circuits within larger units are time-consuming and often performed at a higher unit level, lacking efficiency in testing and verification due to the complexity of constructing dedicated test benches and specifying test vectors.
Innovation Solution
A system and method that utilizes a command line interface to automatically generate a test environment for circuit representations, allowing circuit designers to specify test conditions and simulate circuits, thereby simplifying the verification process by translating command line inputs into test conditions and generating a test bench with logic declarations and common logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated test bench and test vectors are constructed manually for verifying sub-circuits, then verification accuracy is improved, but the time and effort required increases significantly
Solution Approach 1:
The system performs preliminary actions by automatically generating test benches and test vectors from existing circuit descriptions before verification begins. This eliminates the need for manual construction of these test artifacts, maintaining verification accuracy while dramatically reducing the time and effort required.
Solution Approach 2:
The verification system serves itself by automatically creating its own test environment. The circuit description under verification is used to generate the test bench and test vectors, allowing the system to prepare verification artifacts without external human intervention, thus resolving the contradiction between accuracy and time consumption.
2Productivity
If verification is performed at the level of larger units rather than sub-circuits, then verification time is reduced, but verification precision deteriorates
Solution Approach 1:
The system enables segmentation of verification by allowing independent verification of sub-circuits extracted from larger units. The automatic test bench generation works at any hierarchical level, so designers can verify individual sub-circuits in isolation while maintaining high precision, rather than being forced to verify only at the top-level unit.
Solution Approach 2:
The system introduces an intermediary mechanism that automatically generates test benches and vectors, enabling precise sub-circuit verification without requiring manual effort. This intermediary process bridges the gap between verification precision and efficiency, allowing detailed sub-circuit verification to be performed quickly through automated artifact generation.
3Reliability
If manual construction of test benches is performed, then test coverage is improved, but device complexity increases
Solution Approach 1:
The test bench generation process serves itself by automatically creating appropriate test environments from the circuit description. This self-service approach ensures adequate test coverage is achieved without requiring manual construction of complex test benches, as the system autonomously determines and implements the necessary test structure.
Solution Approach 2:
The system creates simplified copies or representations of the circuit under verification as test benches. Rather than manually constructing complex test environments, the automatic generation process creates appropriate test structures that mirror the essential characteristics of the original circuit, achieving good coverage with reduced complexity.
Data Source
AI summary
A system, method, and computer program product are provided for testing a circuit representation. A command line input is received at a command line interface. The command line input is translated into one or more test conditions. Additionally, a test environment configured to simulate the circuit representation and verify the one or more test conditions is generated.