Automated Testbench Generation for Serializer Deserializer Verification
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Solution Overview
Problem
The complexity of high-speed serializer/deserializer (HSS) cores in ASICs, with numerous signal pins and intricate connections, poses challenges for chip designers in instantiating and verifying these cores, and existing methods require writing unique test bench transactors for each system configuration, making it inefficient.
Innovation Solution
A method for automated simulation test bench generation using a database of adaptable transactors, which includes a first transactor for generating raw data, a second for checking encoded data, a third for generating encoded data, and a fourth for checking raw data, allowing for mapping and verification across arbitrary system configurations by selecting a single set of transactors per core, reducing the complexity from an order N2 problem to an order N problem.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unique test bench transactors are written for each system configuration, then verification accuracy is improved, but development complexity and time increase significantly
Solution Approach 1:
The patent creates a universal transactor template that can be automatically configured to work with multiple HSS core types and system configurations. Instead of writing unique transactors for each configuration, a single template with parameterized interfaces and automatic adaptation logic handles diverse configurations, reducing development complexity while maintaining verification accuracy through configuration-specific parameter settings.
Solution Approach 2:
The patent performs preliminary automatic configuration of the transactor template based on the target system configuration before actual verification. By pre-configuring interfaces, data paths, and control signals according to the specific HSS core type and protocol requirements, the system eliminates the need for manual transactor writing for each configuration while ensuring verification accuracy is maintained.
2Reliability
If comprehensive test benches are created for all configurations, then verification coverage is improved, but productivity decreases due to manual writing requirements
Solution Approach 1:
The transactor template is designed to automatically configure itself based on the target system configuration parameters. The template includes self-adaptation logic that automatically adjusts interfaces, data paths, and control mechanisms to match the specific HSS core type and protocol requirements, eliminating manual writing efforts while ensuring comprehensive verification coverage across all configurations.
Solution Approach 2:
The patent uses parameterized configuration to adapt the universal transactor template to different system configurations. By changing parameters such as data width, clock domains, protocol-specific control signals, and interface definitions based on the target configuration, the system achieves comprehensive verification coverage without manual rewriting, significantly improving development efficiency.
3Adaptability or versatility
If the transactor database contains one set per system configuration, then adaptability to specific configurations is improved, but database complexity and maintenance burden increase
Solution Approach 1:
The patent consolidates multiple configuration-specific transactors into a single universal template that can adapt to various HSS core types and system configurations. The template includes parameterized definitions for interfaces, data paths, and control mechanisms that can be configured through parameters rather than requiring separate transactor implementations, reducing database complexity while maintaining adaptability.
Solution Approach 2:
The patent merges multiple configuration-specific transactors into one unified template structure. By combining common functionality and configuration-specific parameters into a single template, the system reduces the database from containing multiple separate transactor sets to a single maintainable template, simplifying database management while preserving configuration adaptability through parameterization.
Data Source
AI summary
Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.