Automated Via Placement for High-Density Chip Package Power Networks

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Solution Overview

Problem

Manual via routing in power distribution networks for chip packages is costly, time-consuming, and prone to human error, especially in high-speed and high-power applications requiring high via density.

Innovation Solution

An automated via placement engine executes a dynamic via placement algorithm to optimize via placement in chip packages, utilizing user input to determine optimal via locations and generate placement instructions, reducing human intervention and improving via density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual via routing is performed using CAD software, then via placement can be completed with human control, but the process becomes costly, time-consuming, and prone to human error

Engineering Contradiction:
Improvevia placement accuracyVSAvoidvia routing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs automated via placement using algorithms that independently determine optimal via locations based on input parameters, eliminating the need for manual human operation in the via routing process while maintaining or improving placement accuracy

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent replaces the manual mechanical process of via routing with an automated computational system that uses algorithms and processors to determine via placements, substituting human manual operations with automated electronic computing

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If via density is increased for high-speed and high-power applications, then power integrity is improved, but the complexity of via routing increases

Engineering Contradiction:
Improvepower integrityVSAvoidvia routing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system dynamically adjusts via placement strategies based on input parameters and application requirements, allowing the routing complexity to adapt to the needed via density while maintaining power integrity through optimized automated placement algorithms

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the approach from manual parameter control to automated parameter optimization, where the system automatically determines optimal via placement parameters based on design requirements, thereby managing complexity while achieving high via density

Inventive Principle:
Principle #35Parameter changes

3Productivity

If automated via placement is implemented, then productivity and consistency are improved, but initial system complexity increases

Engineering Contradiction:
Improvevia placement speedVSAvoidautomation system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The automated system is divided into distinct functional modules including parameter receiving components, processing components that execute placement algorithms, and output components that generate placement data, making the complex automation system manageable and maintainable while achieving high productivity

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4600861A1Method and system of via placement of a dynamic power distribution network in a chip package
Publication Date: 2025.08.13 GOOGLE LLC
  • EP4600861A1 patent drawingFigure 1
  • EP4600861A1 patent drawingFigure 2
  • EP4600861A1 patent drawingFigure 3

AI summary

Aspects of the disclosed technology include a method and a system for an automated process of via placement for a dynamic power distribution network in a chip package. A method for via placement in a chip package includes receiving, by one or more processors, user input defining a working area of the chip package and identifying bump X-Y coordinates and X-Y bump pitches within the defined working area. The one or more processors also identify via location parameters, which are defined by via pad stack design, the bump X-Y coordinates, and the X-Y bump pitches. Then the one or more processors determine via locations for each of a plurality of vias at one or more layers in the chip package based on the identified via location parameters and provide instructions for placing the plurality of vias at the determined via locations in the chip package.