Automatic Addressing Memory Network for Sequence Processing
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Solution Overview
Problem
Current memory neural networks face issues with high memory consumption, slow speed, and inefficient utilization of memory information due to content-based and location-based addressing modes, and the limited ability to effectively utilize memory information in processing units.
Innovation Solution
A memory network method based on automatic addressing and recursive information integration, which uses automatic addressing to read from and write to the memory matrix efficiently, and a novel computing unit that comprehensively computes the hidden state, memory information, and input using three additional gates to control information flow and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If content-based addressing and location-based addressing modes are used for memory reading and writing, then memory can be accessed, but memory consumption increases and processing speed decreases
Solution Approach 1:
The patent extracts the addressing function from traditional content-based and location-based addressing modes, implementing a simplified automatic addressing mechanism that directly maps memory addresses without requiring complex addressing logic tables, thereby reducing memory consumption while maintaining access capability
Solution Approach 2:
The automatic addressing mechanism serves multiple functions: it provides memory addressing, reduces memory consumption, and improves processing speed simultaneously, replacing the need for separate content-based and location-based addressing systems
2Ease of operation
If content-based addressing and location-based addressing modes are used for memory reading and writing, then memory can be accessed, but processing speed decreases due to complex operations
Solution Approach 1:
The patent removes the complex operational steps associated with content-based and location-based addressing, implementing a direct automatic addressing mechanism that computes memory addresses through simple mathematical operations, thereby significantly improving processing speed while maintaining access capability
3Ease of manufacture
If LSTM computing step is simply reused for computing read memory information and hidden-state information, then computation can be performed, but memory information utilization efficiency is low
Solution Approach 1:
The patent transforms the static LSTM computing step into a dynamic information integration mechanism with multiple gates (forget gate, input gate, output gate) that adaptively control information flow based on the importance of memory information, thereby significantly improving memory information utilization efficiency while maintaining computation capability
Data Source
AI summary
A memory network method based on automatic addressing and recursive information integration. The method is based on a memory neural network framework integrating automatic addressing and recursive information, and is an efficient and lightweight memory network method. A memory is read and written by means of an automatic addressing operation having low time and space complexity, and memory information is effectively utilized by a novel computing unit. The whole framework has the characteristics of high efficiency, high speed and high universality. The method is suitable for various time sequence processing tasks, and shows the performance superior to that of the conventional LSTM and the previous memory network.