Automatic Bus Routing in Integrated Circuit Design
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Solution Overview
Problem
Manual routing of buses in integrated circuits is time-consuming and prone to errors, especially when dealing with multiple buses, as traditional signal routers can only route one net at a time, leading to inefficiencies and potential design rule violations.
Innovation Solution
An automatic bus routing method that identifies buses by geometry location adjacency, determines a bus routing area, generates design rule violation-free guidance, and routes the bus as a skinny wire with reserved space for other pins, using a computing device to route multiple nets simultaneously while adhering to design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual routing is used for each net individually, then routing accuracy can be maintained, but routing time increases significantly and productivity decreases
Solution Approach 1:
The patent merges multiple individual net routing operations into a single bus routing operation. By identifying buses through geometry location adjacency and routing multiple nets simultaneously within a determined bus routing area, the system achieves both efficiency and accuracy. The area router generates design rule violation free guidance for the entire bus group, and real bus wire segment embedding ensures accurate routing while meeting design rules.
Solution Approach 2:
The patent creates a universal bus routing methodology that can handle multiple different bus configurations simultaneously. The system identifies buses by geometry location adjacency, determines routing areas using bounding boxes, and applies design rule violation free guidance that works across various bus topologies. This multi-functional approach replaces multiple specialized manual routing operations with a single automated bus routing process.
2Device complexity
If traditional signal routers route one net at a time, then individual net routing simplicity is maintained, but net ordering issues arise and routing complexity increases
Solution Approach 1:
The patent performs preliminary actions by determining the bus routing area using a bounding box of source and destination pins before actual routing occurs. The area router generates design rule violation free guidance in advance, and pin ordering is determined beforehand. This preliminary preparation eliminates net ordering issues during the routing process, as all nets are routed together based on pre-determined ordering within the routing area.
3Adaptability or versatility
If buses are routed manually by selecting paths for each net, then routing flexibility is maintained, but ease of operation decreases and time efficiency is reduced
Solution Approach 1:
The patent implements self-service by enabling automatic bus routing that identifies buses through geometry location adjacency, determines routing areas, and generates design rule violation free guidance without manual intervention. The system automatically routes multiple nets simultaneously while maintaining flexibility through adaptive routing within the determined bus routing area, eliminating the need for manual path selection for each net.
4Productivity
If multiple nets are routed simultaneously as a group, then productivity and time efficiency improve, but routing complexity and design rule compliance difficulty increase
Solution Approach 1:
The patent introduces an area router as an intermediary that generates design rule violation free guidance for bus routing. This intermediary component simplifies the complex task of routing multiple nets simultaneously by providing pre-calculated routing guidance that ensures design rule compliance. The real bus wire segment embedding then follows this guidance to complete the routing, managing complexity while maintaining high productivity.
Data Source
AI summary
Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance between pins and routing layer of the pins. A bus routing area is determined by the bounding box of first group of source pins and a second group of destination pins. Bus routing guidance is then generated by an automatically search engine in the bus routing area. The bus routing guidance models a bus as a skinny wire with large spacing, and it does not violate design rules. Real bus wires are generated based on the bus guidance. A bus is then automatically routed between a first group of source pins and a second group of destination pins based on the bus routing guidance.