Automatic Metastability Fault Analysis in Electronic Design Verification

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Solution Overview

Problem

Current metastability convergence analysis in electronic design verification lacks reliability and scalability due to the need for user-defined properties, leading to performance issues and the state-explosion problem, especially in Clock-Domain Crossing (CDC) designs.

Innovation Solution

A computer-implemented method that automatically generates preconditions to analyze metastability effects at synchronizer outputs, recursively generates properties to propagate these effects through fan-out cones, and visually displays results on annotated graphs to identify metastability convergence points, eliminating the need for user-defined properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual properties are added to model metastability effects in formal verification, then analysis capability is improved, but device complexity and user knowledge requirements increase significantly

Engineering Contradiction:
Improvemetastability analysis capabilityVSAvoidproperty configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs self-service by automatically generating metastability analysis properties without user intervention. The formal verification tool autonomously identifies synchronizers, generates preconditions representing metastability effects, and creates propagation properties, eliminating the need for users to manually configure complex properties while maintaining comprehensive metastability analysis capability

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary action by pre-generating metastability preconditions and properties before the actual verification process. The tool automatically creates the necessary property models and configurations in advance, so that when verification runs, all metastability analysis infrastructure is already in place without requiring user setup

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If simulation-based verification is used for metastability analysis, then ease of operation is maintained, but measurement precision and coverage reliability are insufficient

Engineering Contradiction:
Improveverification operation simplicityVSAvoidmetastability coverage accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The system replaces the mechanical simulation-based verification approach with a formal verification methodology. Instead of relying on simulation metrics that lack precision, the tool uses formal logical reasoning to guarantee metastability coverage, providing mathematically proven analysis while maintaining ease of operation through automatic property generation

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If formal verification with manual properties is used, then metastability analysis precision is improved, but productivity and scalability decrease due to state-explosion problem

Engineering Contradiction:
Improvemetastability analysis accuracyVSAvoidverification scalability
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system applies segmentation by dividing the metastability analysis into distinct automated components: identifying synchronizer locations, generating preconditions for each synchronizer, analyzing fan-out cones, and tracking convergence paths. This structured segmentation enables precise metastability analysis while maintaining scalability through systematic, modular processing that avoids state-explosion

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10769008B1Systems and methods for automatic formal metastability fault analysis in an electronic design
Publication Date: 2020.09.08 CADENCE DESIGN SYST INC
  • US10769008B1 patent drawing
  • US10769008B1 patent drawing
  • US10769008B1 patent drawing

AI summary

The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.