Automatic Mode Reduction for Electronic Circuit Timing Analysis
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Solution Overview
Problem
The complexity of modern electronic circuits requires extensive timing analysis across various modes and corners, leading to a large number of scenarios that are time-consuming and costly to verify, with manual merging of modes being error-prone and impractical due to the large number of constraints.
Innovation Solution
A computer-implemented method and system that automatically determines mergeable modes by comparing pairs of modes, transforming constraints to allow merging, and identifying subsets of modes that can be combined into a single node, reducing the total number of modes to be processed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing analysis is performed for all combinations of modes and corners, then verification completeness is improved, but processing time and cost increase significantly
Solution Approach 1:
The patent merges multiple operating modes into a reduced set of representative modes by comparing timing constraints and identifying equivalent behavior patterns. This combines the verification coverage of multiple modes into fewer analysis scenarios, maintaining reliability while reducing the computational burden of analyzing all mode-corner combinations.
Solution Approach 2:
The patent creates a universal mode representation that can serve multiple original modes simultaneously. By identifying modes with equivalent timing characteristics, a single merged mode can represent the timing behavior of multiple operating conditions, allowing one analysis to validate multiple scenarios.
2Device complexity
If manual merging of modes is performed, then mode reduction is achieved, but error rate and cost increase due to complexity
Solution Approach 1:
The patent implements an automated system that performs mode merging without human intervention. The computer system automatically compares timing constraints, identifies mergeable modes, and generates the reduced mode set, eliminating manual errors while maintaining accuracy through systematic algorithmic analysis of all constraints.
Solution Approach 2:
The patent incorporates verification steps that check whether merged modes preserve the timing characteristics of the original modes. By comparing timing analysis results before and after merging, the system provides feedback to ensure accuracy and can identify cases where modes should not be merged, maintaining reliability throughout the automation process.
Data Source
AI summary
Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode.