Automatic Port Map Elaboration in HDL Design
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Solution Overview
Problem
Current integrated circuit design methodologies require manual entry of complex non-functional-intent structures, such as pervasive logic and clock control, which leads to increased design burden, human error, and degraded simulation performance due to the need for explicit expression of all design elements in HDL files, regardless of their functional intent.
Innovation Solution
A design methodology that supports multiple levels of abstraction, allowing for the automatic elaboration of port maps and reduction of non-functional-intent code, enabling logic designers to focus on functional intent while insulating the design from technology generation changes and accommodating different design preferences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual entry of non-functional-intent structures (pervasive logic, clock control) is required in HDL files, then complete design description is achieved, but design burden and human error increase
Solution Approach 1:
The patent extracts non-functional-intent structures (pervasive logic, clock control structures) from manual HDL entry and handles them automatically through template-based generation. This separation allows designers to focus only on functional intent while the system automatically generates the necessary support structures, reducing design burden and human error.
Solution Approach 2:
The system enables self-service by automatically generating port maps and instantiating pervasive logic structures without requiring manual intervention. The EDA tool autonomously completes the design description by inferring missing port maps from module interfaces and automatically instantiating templates for scan chains, clock control, and other support structures.
2Reliability
If all design elements are explicitly expressed in HDL files, then complete design specification is achieved, but simulation performance degrades
Solution Approach 1:
The patent segments the design model into functional-intent portions (explicitly described by designers) and non-functional-intent portions (automatically generated). This segmentation allows simulation to focus on functional behavior while automatically generated support structures are handled efficiently, improving simulation performance without sacrificing design completeness.
Solution Approach 2:
The system introduces an intermediary layer of template-based generation that bridges the gap between high-level functional descriptions and detailed implementation. This intermediary automatically generates the necessary port maps and support structures, allowing simulation to proceed with complete design specification while maintaining performance through automated rather than manual elaboration.
3Adaptability or versatility
If non-functional-intent structures are manually entered, then design flexibility is maintained, but coding errors increase
Solution Approach 1:
The patent uses template copying to generate non-functional-intent structures. Pre-defined templates for pervasive logic and clock control are automatically instantiated and adapted to the specific design context, ensuring consistency and correctness while maintaining design flexibility. This eliminates manual coding errors while preserving the ability to adapt templates to different design requirements.
4Manufacturing precision
If single level of abstraction is used with full elaboration, then design detail is complete, but simulation performance and coding efficiency suffer
Solution Approach 1:
The patent introduces dynamic abstraction levels where the degree of elaboration can be adjusted based on the design phase and requirements. During early simulation phases, only functional-intent portions are elaborated for fast simulation, while non-functional-intent structures are generated on-demand or in later phases, allowing designers to balance detail completeness with simulation performance and coding efficiency.
Data Source
AI summary
A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.