Automatic Property Generation for Hardware Emulation Debugging
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Solution Overview
Problem
Debugging failures in hardware emulation of integrated circuit designs is challenging due to non-reproducible results and limited debug support, often requiring extensive time and effort to identify the root cause of errors.
Innovation Solution
Automatically generating properties from analysis of a software simulation test suite to aid in debugging hardware emulation, by selecting emulator-synthesizable properties that bound the states traversed during software simulation, allowing for direct incorporation into hardware emulation test suites to detect violations and facilitate quicker diagnosis of emulation failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware emulation is used for verification, then verification speed and capability are improved, but debugging difficulty increases
Solution Approach 1:
The system performs preliminary analysis of software simulation test suites to automatically generate properties and assertions before hardware emulation begins. These pre-generated properties capture expected design behavior and are synthesized into the hardware emulation environment, enabling automated debugging support before emulation failures occur.
Solution Approach 2:
The system introduces an intermediary analysis layer that processes software simulation results and translates them into hardware emulation properties. This intermediary automatically generates assertions and triggers that bridge the gap between software simulation expectations and hardware emulation reality, making debugging easier without sacrificing emulation speed.
2Ease of operation
If software simulation is used for verification, then debugging ease is improved, but verification speed decreases
Solution Approach 1:
The system creates a copy of the design under test in hardware emulation form while using software simulation to generate expected behavior properties. These properties are then synthesized into the hardware emulation, allowing fast verification while maintaining software-like debugging capabilities through automated property checking and trigger generation.
Solution Approach 2:
The system changes the verification parameter from pure software simulation to hardware emulation with synthesized properties. By automatically generating properties from software simulation results and incorporating them into hardware emulation, the system achieves both fast verification speed and maintained debugging ease through automated support.
3Adaptability or versatility
If more transistors are used in integrated circuit design, then design functionality is improved, but verification complexity increases
Solution Approach 1:
The system segments the verification process into distinct phases: software simulation for property generation, automated analysis for property extraction, and hardware emulation for fast verification. This segmentation allows complex designs with many transistors to be verified systematically by breaking down the verification complexity into manageable automated steps.
Solution Approach 2:
The system implements self-service verification by automatically generating properties from software simulation results and synthesizing them into hardware emulation without manual intervention. This automated self-service approach handles verification complexity internally, allowing designers to focus on functionality while the system manages verification complexity automatically.
Data Source
AI summary
Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable for incorporation in a hardware emulation test suite used to test the SoC.