Automatic Rate Realization for Programmable IC Clock Domains
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Solution Overview
Problem
Conventional programmable integrated circuits (ICs) are limited in their ability to efficiently implement multiple data rates within a circuit design, as they typically rely on a single rate realization technique for the entire design, which can lead to increased power consumption and longer implementation times due to the constraints of synchronous clock-based or clock enable-based methods.
Innovation Solution
A computer-implemented method for automatic rate realization in programmable ICs, which compares data rates of clock domains with available clock sources and dynamically selects between multiple synchronous clock and clock enable techniques to optimize clocking, allowing for flexible application of different rate realization methods to each clock domain based on frequency matching, thereby enabling efficient implementation of multiple data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single rate realization technique (multiple synchronous clock or clock enable) is used for the entire circuit design, then the implementation is simpler and more consistent, but power consumption increases and implementation time lengthens due to the constraints of the chosen technique
Solution Approach 1:
The circuit design is segmented into multiple clock domains, each of which can be independently analyzed and assigned an appropriate rate realization technique. The system evaluates each clock domain's data rate requirements and selectively applies either multiple synchronous clock or clock enable techniques to specific domains, rather than forcing a single technique across the entire design. This segmentation allows optimization of power consumption at the clock domain level while maintaining overall system consistency.
Solution Approach 2:
The system dynamically selects the appropriate rate realization technique for each clock domain based on its specific data rate requirements and the available clock sources. Rather than using a static, uniform approach across the entire circuit, the methodology adapts the rate realization technique on a per-clock-domain basis, enabling optimal power efficiency for each domain while maintaining implementation manageability through automated selection.
2Ease of manufacture
If a single rate realization technique is used for the entire circuit design, then the design process is more straightforward and consistent, but implementation time increases due to the limitations of the chosen technique
Solution Approach 1:
The design process is segmented into automated evaluation and selection phases, where the system automatically analyzes each clock domain's requirements and selects the appropriate rate realization technique. This segmentation of the design process maintains simplicity through automation while enabling optimal implementation time for each clock domain by selecting the most efficient technique for its specific requirements.
Solution Approach 2:
The rate realization system performs self-service by automatically evaluating clock domain requirements and selecting appropriate techniques without requiring manual intervention for each domain. The automated methodology assesses data rates, compares available clock sources, and independently determines the optimal rate realization technique for each clock domain, reducing overall implementation time while maintaining design consistency.
3Reliability
If conventional rate realization techniques are used, then the clocking approach is more predictable and easier to manage, but the ability to efficiently implement multiple data rates is limited
Solution Approach 1:
The system dynamically adapts the rate realization technique for each clock domain based on its specific data rate requirements. By evaluating the data rate of each clock domain against available clock sources, the methodology selectively applies multiple synchronous clock or clock enable techniques to achieve efficient implementation of multiple data rates while maintaining predictable and reliable clocking through automated, consistent selection criteria.
Solution Approach 2:
The system changes the parameters of rate realization application by adjusting which technique (multiple synchronous clock or clock enable) is applied to which clock domain based on data rate parameters. This parameter-based selection enables versatile support for multiple data rates while maintaining reliability through systematic, parameter-driven decision-making that ensures appropriate technique assignment for each domain's specific requirements.
Data Source
AI summary
A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.