Autonomous Address Sequencer for Distributed Buffer Memory Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face performance bottlenecks due to bandwidth limitations in communication links between the Host, memory control circuits, data buffer circuits, and memory devices, which impact the efficiency of data storage and retrieval operations.
Innovation Solution
The proposed memory system reduces bandwidth demands by allowing data buffer circuits to autonomously track store data locations without receiving store data tags from the Host or memory control circuit, using synchronized address sequencers to manage data storage and retrieval operations, and implementing periodic tag checks to maintain synchronization and prevent errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If store data tags are transmitted from Host to data buffer circuits over communication links, then data storage operations can be performed, but bandwidth is consumed and communication link load increases
Solution Approach 1:
The data buffer circuit is equipped with an autonomous address sequencer that independently generates store data tags without receiving them from the Host. This self-service mechanism eliminates the need for tag transmission over communication links, freeing up bandwidth while maintaining full data storage functionality.
Solution Approach 2:
The address sequencer functionality is extracted from the Host and placed directly into the data buffer circuit. This extraction removes the dependency on Host-generated tags being transmitted across communication links, thereby reducing bandwidth consumption while preserving the essential address generation capability.
2Reliability
If store data tags are transmitted from memory control circuit to data buffer circuit, then data can be stored at correct locations, but control signal transmissions increase load on communication links
Solution Approach 1:
The data buffer circuit autonomously generates store data tags through its local address sequencer, eliminating the need for the memory control circuit to transmit control signals containing tag information. This self-service approach ensures storage accuracy while reducing control signal complexity.
Solution Approach 2:
The address sequencer pre-generates store data tags locally at the data buffer circuit before data arrival, rather than waiting for tags to be transmitted from the memory control circuit. This preliminary action ensures tags are ready when needed, maintaining storage accuracy without requiring additional control signal transmissions.
3Quantity of substance
If address sequencers are synchronized autonomously without tag transmission, then bandwidth is freed up, but synchronization errors may occur
Solution Approach 1:
A synchronization mechanism provides feedback between the Host's address sequencer and the data buffer circuit's address sequencer. This feedback ensures both sequencers remain synchronized without requiring tag transmission, thereby maintaining synchronization accuracy while preserving bandwidth availability.
Solution Approach 2:
The system employs periodic synchronization checks or reset signals to maintain alignment between distributed address sequencers. This periodic action prevents drift and synchronization errors while allowing autonomous operation that frees up communication bandwidth.
Data Source
AI summary
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.