Autonomous Backside CS and CA Training via RCD

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Solution Overview

Problem

The standardization of memory subsystem processes faces challenges in ensuring reliable command and address signaling due to variations in device geometries, signaling frequencies, and channel layouts, making it difficult for memory devices to operate without training the backside chip select and command/address signal lines, which requires significant host intervention and firmware complexity.

Innovation Solution

An autonomous Register Clock Driver (RCD) is used to train the backside chip select and command/address signal lines independently, eliminating the need for host intervention by triggering the DRAMs into training mode, driving signal lines with patterns, and adjusting parameters based on feedback received over a sideband bus, allowing parallel training of all DIMMs and ranks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the host memory controller trains the backside chip select and command/address signal lines, then reliable command and address signaling is achieved, but host intervention and firmware complexity increase significantly

Engineering Contradiction:
Improvecommand and address signaling reliabilityVSAvoidhost intervention and firmware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The RCD autonomously performs training of the backside chip select and command/address signal lines without requiring host memory controller intervention. The RCD includes training logic that automatically adjusts timing parameters and controls the training process, enabling the system to self-configure after boot-up without complex firmware involvement.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The training functionality is extracted from the host memory controller and relocated to the RCD itself. By moving the training logic to the RCD, the host controller is freed from the complex task of coordinating training sequences, reducing host intervention requirements while maintaining reliable signaling.

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If traditional host-controlled training is used, then signaling accuracy is ensured, but training time during system boot increases

Engineering Contradiction:
Improvesignaling accuracyVSAvoidtraining time during system boot
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The RCD performs training actions automatically and autonomously during the boot-up sequence without waiting for host controller commands. By initiating and completing training independently in the background, the system reduces the visible training time and accelerates the boot process while maintaining signaling accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The RCD's autonomous training capability allows it to complete signaling calibration independently without host coordination, significantly reducing the time the system spends in training mode during boot-up while ensuring accurate signal transmission.

Inventive Principle:
Principle #25Self-service

3Reliability

If multiple MPC commands are used for training, then comprehensive signal line training is achieved, but the number of host cycles and firmware complexity increase

Engineering Contradiction:
Improvesignal line training completenessVSAvoidhost cycles and training efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The training commands and control logic are extracted from the host memory controller's MPC command set and implemented within the RCD's autonomous training logic. This eliminates the need for multiple host cycles to issue and process training commands, improving productivity while maintaining comprehensive training coverage.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The RCD acts as an intermediary that manages the training process internally using its own control logic and timing mechanisms. Instead of the host controller directly controlling each training step through multiple commands, the RCD's internal training logic coordinates the entire process, reducing host cycle requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20220300197A1Autonomous backside chip select (CS) and command/address (CA) training modes
Publication Date: 2022.09.22 INTEL PRODUCTS IP LLC
  • US20220300197A1 patent drawing
  • US20220300197A1 patent drawing
  • US20220300197A1 patent drawing

AI summary

Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.