Autonomous Clock Management for Display Subsystems
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Solution Overview
Problem
Existing clock management in electronic circuitry, particularly in display subsystems of computers, is inefficient due to software-based control, which increases complexity and latency, and may lead to hardware conflicts and inefficiencies in disabling idle circuitry.
Innovation Solution
A system with a software interface circuit that autonomously determines which hardware components will be idle or functional in an upcoming period, enabling or disabling clocks accordingly, thereby reducing latency and preventing conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If software component controls clock enabling and disabling, then power savings can be achieved, but software complexity increases and latency increases
Solution Approach 1:
A hardware intermediary circuit is introduced between the software and the clock generator. This hardware circuit receives control signals from the software and autonomously manages the enabling and disabling of clocks to various circuit blocks, eliminating the need for complex software logic while maintaining power management functionality
Solution Approach 2:
The patent replaces the software-based clock management system with a hardware-based system. The hardware circuit directly controls the clock generator based on simple control signals, substituting the software control mechanism with a faster, simpler hardware mechanism that reduces both complexity and latency
2Loss of energy
If software component manages clock disabling, then power savings are possible, but response time increases due to software processing delay
Solution Approach 1:
The patent replaces the software-based clock management system with a hardware-based system. The hardware circuit directly controls the clock generator based on simple control signals, substituting the software control mechanism with a faster, simpler hardware mechanism that reduces both complexity and latency
3Loss of energy
If software determines idle circuitry, then clocks can be disabled for power savings, but hardware conflicts may occur due to software unawareness of exact hardware state
Solution Approach 1:
A hardware intermediary circuit is introduced between the software and the clock generator. This hardware circuit receives control signals from the software and autonomously manages the enabling and disabling of clocks to various circuit blocks, eliminating the need for complex software logic while maintaining power management functionality
Solution Approach 2:
The hardware circuit monitors the state of circuit blocks and provides feedback control for clock enabling/disabling decisions, ensuring that clocks are only disabled when the circuit block is truly idle and will not be accessed, thus preventing hardware conflicts
Data Source
AI summary
A system and method for enabling or disabling clocks to one or more portions of hardware circuitry, for example a display sub-system of a personal computer. A processor generates a command or data to a first circuit configured to perform a function based at least on the command or data. A clock generator selectively supplies clocks to the first circuit and a second circuit configured to perform a second function. A software interface circuit coupled to the processor and the clock generator autonomously determines based at least on the command or data whether the second circuit will perform the second function or be idle in an upcoming period and disables one or more of the clocks to the second circuit if the second circuit will be idle in the upcoming period.