Autonomous Clock Generation Circuit for Low-Frequency Control
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Solution Overview
Problem
Existing clock signal generation circuits burden the central processing unit (CPU) and lead to increased system size due to the CPU's involvement in controlling clock signal frequencies, especially when generating low-frequency signals, which requires large capacitors and resistors in analog circuits.
Innovation Solution
A clock signal generation circuit that includes an oscillating circuit, a counter, a subtracting circuit, and a digital-analog converter, allowing for independent operation without CPU control, using a switch and timing control circuit to manage clock signal frequencies and reduce system size by eliminating the need for high-capacity components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CPU controls the clock signal frequency, then the clock frequency can be adjusted, but the CPU burden increases and system size increases
Solution Approach 1:
The patent divides the clock control function into two independent parts: a digital control section (counter and subtracting circuit) that operates autonomously without CPU intervention, and an analog adjustment section (DAC and oscillating circuit) that handles frequency calibration. This segmentation allows the digital section to manage basic frequency control independently while the analog section provides precise adjustment, thereby reducing CPU burden and system complexity.
Solution Approach 2:
The patent introduces a digital-analog converter (DAC) as an intermediary component between the digital control signal and the analog oscillating circuit. The DAC translates digital control values into analog voltage signals that directly adjust the oscillating circuit's frequency, eliminating the need for CPU-mediated control and reducing system complexity while maintaining frequency adjustment capability.
2Measurement precision
If large capacitors and resistors are used in analog circuits to generate low-frequency clock signals, then accurate low-frequency generation is achieved, but system size increases
Solution Approach 1:
The patent changes the control parameter from direct analog component values (large capacitors and resistors) to digital control values that are converted to analog signals via DAC. By using the DAC to generate precise voltage levels from digital codes, the system achieves accurate low-frequency clock generation without requiring physically large analog components, thereby maintaining frequency precision while reducing system size.
3Adaptability or versatility
If the CPU is involved in clock signal control, then frequency presetting is possible, but the operation speed of the entire system deteriorates
Solution Approach 1:
The patent implements preliminary action by pre-calculating and storing frequency control values in a register before actual clock generation is needed. When frequency adjustment is required, the pre-computed digital control value is simply loaded into the register and automatically converted by the DAC, eliminating the need for real-time CPU calculation and intervention during critical timing operations, thus maintaining high system operation speed while preserving frequency presetting capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the CPU's burden, prevents system size increase, and allows for accurate clock signal frequency control without CPU intervention, even at low frequencies, by using a switch and timing control circuit to manage clock signal frequencies and eliminate the need for large capacitors and resistors.
Implementation Method 1
The oscillating circuit 122 is configured to generate a clock signal CLK having a preset frequency in accordance with a control signal outputted from the digital-analog converter (DAC) 116. This oscillating circuit 122 can be constituted by, for example, a voltage-controlled oscillator (VCO) and generates a clock signal having a frequency corresponding to a voltage signal outputted from the digital-analog converter (DAC) 116.
Implementation Method 2
A digital-analog converter (DAC) 116 converts the digital control signal outputted from the central processing unit (CPU) 130 into an analog signal and outputs the converted analog signal to the oscillating circuit 122.
Data Source
AI summary
According to a preferred embodiment, a clock signal generation circuit includes an oscillating circuit configured to output a clock signal having a clock frequency corresponding to a control signal, a counter configured to generate a count value by counting a pulse number of the clock signal outputted from the oscillating circuit during a predetermined time period, a subtracting circuit configured to produce differential data by subtracting the count value from a preset value previously set based on a predetermined clock frequency, a control signal correcting circuit configured to generate a correcting control signal by correcting a value of the control signal based on the differential data, and a digital-analog converter circuit configured to convert the correcting control signal into an analog correcting control signal and output the converted analog correcting control signal to the oscillating circuit. This clock signal generation circuit can prevent increasing of the circuit size or the system size due to a resistor, a capacitor element, etc., used in a PLL (Phase Locked Loop) without using a central processing unit.