Autonomous Configuration Loading in Reconfigurable Dataflow Processors

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Solution Overview

Problem

Existing systems for loading configuration files into reconfigurable data processors, such as coarse-grained reconfigurable architecture (CGRA) processors, are inefficient as they require significant host processor resources and waste time when the CGR processor is idle, waiting for host processor scheduling.

Innovation Solution

Implement a method where the CGR processor autonomously loads successive configuration files by using information included in the current configuration file, allowing it to proceed with execution without waiting for the host processor. This involves pre-loading configuration files and associated argument load files into memory by a host computer and using configuration load circuitry within the CGR processor to manage the loading process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the host processor loads configuration files into the CGR processor, then the CGR processor can execute configuration files, but the CGR processor must wait idle for host processor scheduling

Engineering Contradiction:
ImproveCGR processor execution capabilityVSAvoidCGR processor idle waiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The host processor pre-loads multiple configuration files and argument load files into the CGR processor's memory before execution begins. This preliminary action ensures that when the CGR processor completes one configuration file, subsequent configuration files are already available in memory, eliminating idle waiting time and enabling continuous execution.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the host processor manages configuration file loading, then configuration files can be loaded into the CGR processor, but significant host processor resources are consumed

Engineering Contradiction:
ImproveConfiguration file loading capabilityVSAvoidHost processor resource consumption
Core Design Contradiction:
Ease of operationVSUse of energy by moving object

Solution Approach 1:

The configuration file loading and management functionality is extracted from the host processor and implemented as dedicated circuitry within the CGR processor itself. This extraction transfers the resource-intensive loading operations to the CGR processor's own hardware, reducing host processor resource consumption while maintaining ease of operation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The CGR processor is equipped with self-service capabilities through integrated configuration load circuitry that can autonomously manage the loading and execution of configuration files without continuous host processor intervention. This self-service mechanism reduces dependency on the host processor and minimizes resource consumption.

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If the CGR processor waits for host processor scheduling, then configuration files can be loaded sequentially, but the CGR processor cannot operate continuously

Engineering Contradiction:
ImproveSequential configuration loadingVSAvoidCGR processor continuous operation
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The system enables continuous useful action by pre-loading multiple configuration files into the CGR processor's memory before execution. As the CGR processor completes each configuration file, the next file is already available, allowing seamless continuous operation without interruption or idle waiting for host processor scheduling.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250077239A1Hardware layer-by-layer program control in a reconfigurable dataflow processor
Publication Date: 2025.03.06 SAMBANOVA SYSTEMS INC
  • US20250077239A1 patent drawing
  • US20250077239A1 patent drawing
  • US20250077239A1 patent drawing

AI summary

A reconfigurable data processor includes a bus system, an array of configurable units, and a configuration load controller connected to the bus system and coupled to a memory. The configuration load controller incorporates a first set of registers accessible from a host processor for storing addresses of a first configuration file, a second set of registers loaded by loading a configuration file for storing addresses of a second configuration file, and an address generation unit with working address registers. The processor is configured to load a first configuration file from the memory and initiate execution based on a request from runtime software. Additional configuration files are automatically loaded upon completion of a previous configuration file based on information stored in the previous configuration file.