Autonomous Core Perimeter for Low Power Processor State Transitions
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Solution Overview
Problem
Modern processors face significant latency and performance issues when transitioning to low power states due to the need to save and restore working state information and firmware, which can result in unacceptable delays and prevent frequent power state changes, especially in mobile devices where battery life is a concern.
Innovation Solution
The implementation of an autonomous core perimeter that coordinates the saving and restoring of microcontroller state information and firmware images across multiple cores, allowing for efficient transition to and from low power states by minimizing data transfer and latency through a high-speed internal bus interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor transitions to low power states to save energy, then battery life is extended, but latency and performance degradation occur due to data transfer requirements
Solution Approach 1:
The patent divides the processor into multiple independent cores, each with its own autonomous core perimeter logic. This segmentation allows individual cores to enter low power states independently without requiring synchronization across all cores, enabling finer-grained power management that reduces overall transition latency and improves energy efficiency.
Solution Approach 2:
The autonomous core perimeter logic acts as an intermediary between the core processing logic and external memory. It caches frequently accessed data and coordinates save/restore operations locally, reducing the need for external data transfers during power state transitions and thereby minimizing latency while maintaining energy savings.
2Adaptability or versatility
If working state information and firmware are saved to external memory, then power states can be transitioned, but data transfer overhead and latency increase
Solution Approach 1:
The patent extracts the power state management functions from the core processing logic and places them in the autonomous core perimeter logic. This extraction allows the perimeter logic to handle save/restore operations independently, simplifying the overall system architecture by separating power management complexity from the core processing functions.
Solution Approach 2:
The autonomous core perimeter logic performs preliminary actions by caching frequently accessed data and pre-coordinating save/restore operations before power state transitions are required. This proactive approach reduces the data transfer overhead during actual transitions and simplifies the coordination complexity.
3Loss of energy
If multiple cores are placed in low power states, then overall power consumption decreases, but coordination complexity and data transfer requirements increase
Solution Approach 1:
Each core's autonomous core perimeter logic independently manages its own power state transitions and data save/restore operations. This self-service capability eliminates the need for centralized coordination between cores, allowing multiple cores to enter low power states independently while reducing overall system power consumption without increasing coordination complexity.
Data Source
AI summary
Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.