Autonomous DRAM Scrubbing via Refresh-Triggered RMW Operations
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Solution Overview
Problem
Contemporary memory systems face high overhead and complexity in ensuring all data locations in DRAM are scrubbed for single bit errors, with the memory controller managing scrub operations and lacking visibility into error counts, which can lead to uncorrectable errors if single bit flips accumulate.
Innovation Solution
Implementing autonomous DRAM scrubbing triggered by refresh commands, where the DRAM performs read/modify/write operations to correct single bit errors and increment error counts, eliminating the need for memory controller management and allowing for alerts when error thresholds are exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller manages scrub operations systematically, then all memory locations can be scrubbed, but overhead and complexity increase significantly
Solution Approach 1:
The patent implements autonomous scrubbing within the DRAM device itself, where the DRAM performs self-diagnosis and self-correction of single-bit errors without requiring external controller management. The scrub logic is integrated into the DRAM, allowing it to autonomously execute scrub operations on its own memory locations, thereby eliminating the overhead and complexity that would otherwise reside in the memory controller.
2Reliability
If the memory controller manages scrub operations, then scrubbing can be performed, but mainline bandwidth is occupied and productivity decreases
Solution Approach 1:
By integrating scrub logic directly into the DRAM device, the patent enables autonomous scrub operations that do not require memory controller intervention. This self-service approach allows scrubbing to occur independently using internal resources, thereby freeing up mainline bandwidth for other memory operations and improving overall system productivity.
Solution Approach 2:
The patent performs scrub operations as part of the regular refresh sequence, utilizing the existing refresh infrastructure to carry out error detection and correction. By embedding the scrub function within the refresh operation, the system prepares and maintains memory reliability proactively without requiring separate scrub commands that would consume bandwidth.
3Loss of information
If error counts are tracked autonomously in DRAM, then visibility into error conditions is improved, but device complexity increases
Solution Approach 1:
The patent implements a multi-functional scrub logic unit within the DRAM that simultaneously performs error detection, error correction, and error counting. This universal component handles multiple tasks using a single integrated structure, thereby improving error visibility without proportionally increasing device complexity. The scrub logic leverages existing ECC infrastructure while adding counting functionality.
Data Source
AI summary
An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.