Autonomous Memory Die Testing Mechanism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The time-consuming process of testing memory dies during the development and manufacturing phases is largely due to communication and data transfer between the personal computer, integrated circuit tester, and memory die, which can be optimized for faster results.
Innovation Solution
Implementing an autonomous testing mechanism within the memory die assembly that can perform multiple test cycles independently, reducing the need for external management and communication, thereby speeding up the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory die is tested for many cycles using external testing equipment, then the reliability of data storage is verified, but the testing time increases significantly
Solution Approach 1:
The memory die incorporates an autonomous testing mechanism that enables it to perform self-testing without requiring external testing equipment. The test controller within the memory die manages test cycles internally, allowing the memory die to verify its own reliability through multiple programming and reading cycles autonomously, thereby reducing the time needed for external testing while maintaining reliability verification
Solution Approach 2:
The memory die performs preliminary testing during its own operation before being subjected to extensive external testing. By conducting initial reliability verification through autonomous multiple-cycle testing, the system can identify and filter out defective memory dies early in the process, reducing the burden on subsequent external testing phases
2Reliability
If the memory die is tested for many cycles during development phase, then the operation reliability under various conditions is verified, but the development cycle is slowed down
Solution Approach 1:
The memory die performs self-verification of operation reliability through autonomous testing cycles. The test controller executes programming and reading operations multiple times internally, allowing the development team to verify reliability claims without requiring prolonged external testing, thus maintaining development momentum while ensuring operational reliability
Solution Approach 2:
The memory die incorporates feedback mechanisms where the test controller monitors the results of programming and reading operations during autonomous testing cycles. This feedback allows real-time verification of reliability under various conditions without requiring external intervention, enabling rapid validation of development claims
3Reliability
If the memory die is tested for many cycles during manufacturing phase, then the fabrication defects are screened, but the manufacturing process is slowed down
Solution Approach 1:
The memory die performs autonomous self-testing during manufacturing, with the test controller executing multiple testing cycles internally without requiring external testing equipment. This self-service approach allows rapid screening of fabrication defects while maintaining manufacturing speed, as the memory die verifies its own reliability through integrated testing rather than requiring separate external testing steps
Solution Approach 2:
The testing function is merged with the memory die structure itself, combining the storage array and test controller into a single integrated unit. This integration allows testing operations to be performed concurrently with manufacturing processes, eliminating the need for separate external testing steps and thereby maintaining high manufacturing throughput while ensuring reliability
Data Source
AI summary
A memory die assembly, comprising a non-volatile memory structure, performs autonomous testing of the memory die assembly by repeatedly performing a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure. Failure events from the tests are recorded by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event, a type of test that failed and a cycle during which the failure event occurred.