Autonomous Ferroelectric Memory Latch for Power-Disruption Logic State
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Solution Overview
Problem
Existing logic circuits that operate across power disruptions face challenges in maintaining system state due to limitations in energy storage and the need for separate save/restore modes, especially when using non-volatile memory devices that operate at different logic levels or frequencies, leading to complexity and cost.
Innovation Solution
A circuit with an autonomous memory latch (AML) that includes a ferroelectric capacitor, a conductive load, and a switch with a current-actuated control input, allowing the circuit to preserve its state across power disruptions by using a feedback loop and switch control to manage power transitions, ensuring the state is not altered during power instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory operates at different logic levels or frequencies than the circuitry, then the memory can store system state, but the memory cannot track the state in real time and requires separate save/restore modes
Solution Approach 1:
The patent changes the operating parameters of the non-volatile memory to match the logic levels and frequencies of the circuitry, enabling real-time state tracking without separate save/restore modes. This parameter alignment allows the memory to operate synchronously with the circuitry while maintaining non-volatile storage capabilities.
2Speed
If ferroelectric memory devices operate at the same logic levels as circuitry, then they can be read and written quickly, but preventing data alteration during power instability becomes challenging
Solution Approach 1:
The patent introduces a switch as an intermediary component between the ferroelectric memory and the circuitry. This switch acts as a gatekeeper, controlling when the memory is connected to the circuitry and preventing unwanted write operations during power instability. The switch enables the memory to operate at full speed during normal operation while protecting data integrity during power disruptions.
3Reliability
If a separate save/restore mode is used, then the system can preserve state across power disruptions, but the system complexity and cost increase
Solution Approach 1:
The patent merges the save/restore functionality into the normal operation of the system by aligning the memory operating parameters with the circuitry. This integration eliminates the need for separate save/restore modes, as the memory continuously tracks the system state in real-time while maintaining non-volatile storage, thereby reducing system complexity and cost.
4Duration of action of moving object
If energy storage such as a battery is used to maintain system state, then the circuit can operate across power disruptions, but the system is limited by the amount of power that can be stored
Solution Approach 1:
The patent replaces the mechanical/chemical energy storage system (battery) with an electronic non-volatile memory system. This substitution eliminates the limitations of stored power capacity while maintaining the ability to preserve system state across power disruptions. The non-volatile memory requires no power to maintain data, allowing indefinite operation duration without being constrained by battery capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The AML circuit effectively maintains the system state during power disruptions without the need for separate save/restore modes, reducing complexity and cost by operating at the same logic levels as the circuitry and synchronously reading/writing, thus preventing data alteration during power fluctuations.
Implementation Method 1
A circuit with an autonomous memory latch (AML) that includes a ferroelectric capacitor
Implementation Method 2
a switch with a current-actuated control input, allowing the circuit to preserve its state across power disruptions by using a feedback loop and switch control
Data Source
AI summary
A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.