Autonomous PWM Waveform Generation Without CPU Intervention
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Solution Overview
Problem
Existing PWM modules in micro-controller units (MCUs) require CPU intervention for dynamic setting changes, leading to high power consumption and limitations in pattern generation due to slow memory-mapped interfaces and real-time requirements.
Innovation Solution
A digital microprocessor device with a counter and comparator module that automatically loads parameters from memory without CPU intervention, allowing for autonomous alteration of output signals, including duty cycle and polarity, to generate complex waveforms with reduced power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CPU is used to dynamically change PWM settings, then flexibility in waveform generation is improved, but power consumption increases and real-time performance deteriorates
Solution Approach 1:
The PWM module is designed to autonomously load parameters from memory and generate waveforms without requiring CPU intervention. The module self-manages parameter loading, counter operation, and waveform generation, eliminating the need for continuous CPU involvement and thereby reducing power consumption while maintaining waveform generation flexibility.
Solution Approach 2:
The system separates the PWM generation function from the CPU, creating an independent PWM module with its own parameter storage and control logic. This segmentation allows the PWM module to operate autonomously using dedicated hardware resources, reducing the power burden on the CPU while maintaining adaptability through separate parameter control.
2Adaptability or versatility
If CPU loads parameters sequentially from memory, then parameter updates are possible, but real-time performance deteriorates due to slow memory-mapped interface
Solution Approach 1:
The PWM module autonomously loads parameters from memory without requiring sequential CPU access. The module independently manages parameter retrieval and application, eliminating the slow sequential loading bottleneck and enabling real-time waveform generation with updated parameters.
Solution Approach 2:
The invention introduces an intermediary mechanism where the PWM module directly accesses memory parameters without CPU mediation. This intermediary approach bypasses the slow memory-mapped interface bottleneck by establishing a direct parameter loading path from memory to the PWM module, enabling real-time performance.
3Adaptability or versatility
If CPU must be powered up from dormant state to change settings, then parameter changes are possible, but power consumption significantly increases
Solution Approach 1:
The PWM module is designed to remain operational and autonomously manage parameter changes without requiring CPU power-up from dormant state. The module continuously monitors and updates parameters from memory, maintaining adaptability while keeping the CPU in a low-power state.
Solution Approach 2:
The system implements dynamic parameter updates where the PWM module can change settings in real-time without static CPU intervention. This dynamic operation allows the CPU to remain dormant while the PWM module adapts waveforms autonomously, significantly reducing overall power consumption.
4Adaptability or versatility
If multiple comparators are used to generate complex patterns, then waveform complexity is improved, but device complexity increases
Solution Approach 1:
The PWM module uses a universal comparator that can generate multiple output waveforms with different patterns simultaneously. This single multi-functional comparator replaces what would otherwise require multiple separate comparators, reducing device complexity while maintaining the ability to generate complex waveform patterns through software-controlled parameter variations.
Data Source
AI summary
A digital microprocessor device (2) has: a central processing unit; a memory (8); and an output signal module (4). The output signal module comprises: a counter (6) arranged to count to a predetermined count value; and at least one comparator (10a, 10b, 10c) arranged to change an output signal (14a, 14b, 14c) from a first output state to a second output state when the counter reaches a predetermined comparator value. The output signal module is arranged to load automatically from the memory at least one parameter selected from the group comprising: the predetermined count value, the predetermined comparator value and the first output state or the second output state, without receipt of an instruction from the central processing unit.


