Autosleep Voltage Regulator Circuit for Low Standby Current
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Solution Overview
Problem
Integrated circuits face challenges in reducing power consumption during sleep modes, especially when a separate power supply pin for digital logic is not available, leading to significant current consumption due to the internal voltage regulator remaining active.
Innovation Solution
The integration of autosleep logic circuitry with a voltage regulator that includes a latch and delay timer, allowing the voltage regulator to turn off when no activity is detected at the input terminals for a specified time, thereby reducing standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the internal voltage regulator remains active to provide power supply voltage, then the digital logic can be powered down, but significant current is consumed by the voltage regulator in sleep mode
Solution Approach 1:
The voltage detection circuit detects the power supply voltage level in advance and sets the latch before the sleep mode is fully entered, ensuring that the voltage regulator is turned off at the appropriate time while maintaining power supply stability through the previously stored voltage state in the latch
Solution Approach 2:
The voltage detection circuit continuously monitors the power supply voltage and provides feedback to the latch, which controls the voltage regulator's on/off state. This feedback mechanism ensures that the voltage regulator remains off as long as the voltage threshold is met, minimizing standby current while maintaining reliability
2Loss of energy
If a separate power supply pin for digital logic is provided, then the digital logic can be powered down independently, but the device complexity and pin count increase
Solution Approach 1:
The existing power supply pin serves dual purposes: it provides power to both the voltage regulator and the digital logic during normal operation, and it enables the voltage detection function during sleep mode. This multi-functionality eliminates the need for a separate power supply pin while achieving independent power down capability
Solution Approach 2:
The voltage detection circuit uses the existing power supply voltage to detect and control the voltage regulator's state, eliminating the need for additional control pins or external components. The system serves itself by using its own power supply signal to trigger the sleep mode sequence
3Loss of energy
If the voltage regulator is turned off to reduce standby current, then power consumption decreases, but the power supply voltage is not available when needed
Solution Approach 1:
The delay timer provides a time delay that allows the voltage regulator to remain off during extended sleep periods, while the latch maintains the off state. When activity is detected, the system is already prepared to quickly reactivate the voltage regulator, minimizing the impact on power-up response time
Solution Approach 2:
The system dynamically adjusts the voltage regulator's state based on real-time detection of input activity. The delay timer creates a dynamic transition period that balances between maintaining low standby current and ensuring rapid power-up when needed, making the power management adaptive rather than static
Data Source
AI summary
An integrated circuit including an autosleep circuit and a voltage regulator. The autosleep circuit includes a latch, a voltage detection circuit outputting a signal to a set input of the latch responsive to a voltage at its input exceeding a threshold voltage, and a delay timer outputting a signal to a reset input of the latch responsive to inactivity at one or more input terminals. A voltage regulator is configured to generate a voltage for biasing a subsystem such as digital logic, and is also the input voltage to the voltage detection circuit. The voltage regulator includes a plurality of transistors in parallel, one gated by the output of the latch and each of the others gated by one of the one or more input terminals. The voltage regulator includes an output leg that generates the output voltage responsive to one of the parallel transistors being turned on.