Auxetic Semiconductor Microstructures for 3D Memory Warpage
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Solution Overview
Problem
Semiconductor structures, particularly in three-dimensional memory devices, face warpage issues due to asymmetric stress from metal word lines, leading to a 'saddle' shape that affects device performance and reliability.
Innovation Solution
Incorporating auxetic microstructures with a negative Poisson's ratio into the semiconductor substrate or over it, which reduces warpage by opposing stresses along different directions, thereby stabilizing the substrate's shape and improving device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal word lines are used in three-dimensional memory devices, then electrical connectivity and device functionality are improved, but substrate warpage and structural stability deteriorate
Solution Approach 1:
The patent applies local quality by creating auxetic microstructures with specific geometric patterns (e.g., re-entrant honeycomb, rotated square) in localized regions of the substrate. These microstructures have different mechanical properties than the bulk material, providing negative Poisson's ratio behavior in specific areas to counteract warpage while maintaining overall substrate integrity and device functionality.
Solution Approach 2:
The patent employs composite materials by combining the auxetic microstructure pattern with the substrate material (e.g., silicon, silicon-germanium). This composite approach creates a material with tailored mechanical properties, specifically achieving negative Poisson's ratio behavior that opposes the asymmetric stress from metal word lines and reduces warpage while maintaining electrical connectivity.
2Stability of the object's composition
If auxetic microstructures are incorporated into the substrate, then substrate warpage is reduced and structural integrity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the substrate into regions containing repeated auxetic microstructure units. Each unit cell (e.g., re-entrant honeycomb cell, rotated square element) is a simplified geometric pattern that, when tiled across the substrate, creates the overall auxetic behavior. This segmentation reduces manufacturing complexity compared to creating a monolithic complex structure.
Solution Approach 2:
The patent utilizes another dimension by implementing the auxetic microstructures in the planar (x-y) dimension of the substrate rather than adding complexity in the vertical (z) dimension. The microstructures are formed as two-dimensional patterns within the substrate plane, which can be integrated with existing planar fabrication processes, thereby reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The incorporation of auxetic microstructures effectively reduces substrate warpage, enhancing the structural integrity and performance of semiconductor devices by mitigating stress-induced deformations, particularly when the lateral to vertical dimension ratio is greater than 10.
Implementation Method 1
Auxetic structures refer to a structure exhibiting a negative Poission's ratio. When stretched along a first direction, an auxetic structure becomes thicker along a second direction that is perpendicular to the first direction. When compressed along the first direction, the auxetic structure becomes thinner along the second direction.
Data Source
AI summary
A semiconductor structure includes a semiconductor device substrate, and an auxetic microstructure containing an auxetic matrix having a negative Poission's ratio.