Auxetic Semiconductor Array for Stretchability Without Fill Factor Loss
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Solution Overview
Problem
Current stretchable semiconductor arrays face challenges in achieving high area density and maintaining electrical performance under large mechanical deformations, limiting their integration into practical applications such as cameras and photovoltaics.
Innovation Solution
A deformable array of semiconductor devices with an auxetic geometry, featuring a tunable structural design that enables synclastic bending over non-linear surfaces, utilizing high fill factor units with active interconnects and sidewall PN junctions to increase active area density and retain electrical performance under deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wavy serpentine structures are used to enable stretchability, then the semiconductor can accommodate large mechanical deformations, but the area coverage and fill factor are reduced
Solution Approach 1:
The patent applies synclastic curvature (dome-shaped bending) to the semiconductor structure, allowing it to conform to convex surfaces while maintaining area coverage. This differs from traditional wavy/serpentine approaches by using controlled 3D curvature that preserves fill factor while enabling stretchability through geometric reconfiguration.
Solution Approach 2:
The patent transitions from 2D wavy patterns to 3D synclastic bending, utilizing out-of-plane curvature to achieve stretchability without sacrificing in-plane area coverage. This dimensional approach allows the structure to expand in multiple directions while maintaining high fill factor.
2Adaptability or versatility
If the semiconductor is made flexible and stretchable, then it can conform to non-linear surfaces, but maintaining electrical performance under large deformation becomes difficult
Solution Approach 1:
The patent employs thin-film semiconductor structures that can be elastically deformed while maintaining electrical integrity. The thin-film nature allows flexible bending and stretching without cracking, preserving electrical performance through elastic recovery.
Solution Approach 2:
The patent modifies geometric parameters (curvature radius, thickness, pattern dimensions) to optimize the balance between flexibility and electrical performance. By controlling these parameters, the structure can undergo large deformations while keeping strain within acceptable limits for maintaining electrical functionality.
3Adaptability or versatility
If traditional serpentine interconnects are used, then stretchability is achieved, but the area density and fill factor are low
Solution Approach 1:
The patent merges the interconnect function with the active device structure itself, eliminating the need for separate serpentine interconnects. The active mass is directly patterned into synclastic geometries that provide both structural flexibility and electrical connectivity, thereby increasing area density and fill factor.
Solution Approach 2:
The synclastic structure serves multiple functions simultaneously: it provides mechanical flexibility, electrical connectivity, and active device functionality. This multi-functionality eliminates the need for dedicated interconnect structures, maximizing area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The auxetic geometry allows semiconductor devices to stretch and flex beyond their intrinsic tensile strain limits, maintaining high area coverage and electrical performance, enabling conformal bending around convex and bumpy surfaces, and enhancing photo-conversion efficiency in solar cells.
Implementation Method 1
The array has an auxetic geometry. The design allows every component of a device to be fabricated into periodic arrangement of high fill factor units composed of device active masses connected by active interconnects which retain their electrical performance under large levels of mechanical deformation.
Implementation Method 2
a tunable structural design that enables inorganic and organic semiconductor devices to become highly flexible, and stretchable, and exhibit synclastic bending over non-linear surfaces
Implementation Method 3
For an embodiment where the devices are solar cells, the structure further increases active area density through the introduction of a sidewall PN junction, enhancing photo-conversion efficiency in solar cells.
Data Source
AI summary
A deformable array of semiconductor devices, and a method of manufacturing such a deformable array. The deformable array comprises a plurality of islands, where each island contains at least one semiconductor device, and the plurality of islands are arranged in an auxetic geometry.