Active Matrix Substrate Auxiliary Capacitor Line Intersection Alignment

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Solution Overview

Problem

The PSA step under the Cs-COM voltage application scheme causes disturbances in liquid crystal alignment at the intersection of pixel electrode slits and auxiliary capacitor lines, leading to defects in pretilt angle formation and subsequent deterioration in display quality.

Innovation Solution

An active matrix substrate with a metal layer covering the auxiliary capacitor line or scanning signal line at intersections, allowing for controlled potential states that block the influence of equipotential surfaces and maintain proper liquid crystal alignment during both manufacturing and operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If voltage is applied during PSA step under Cs-COM scheme, then liquid crystal alignment is controlled, but alignment disturbances occur at intersection of pixel electrode slits and auxiliary capacitor lines

Engineering Contradiction:
Improvepretilt angle formation accuracyVSAvoidalignment uniformity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies different potential states to different regions of the auxiliary capacitor line. Specifically, the auxiliary capacitor line is divided into multiple potential regions with different potentials, allowing the intersection areas with pixel electrode slits to have optimized potential conditions that prevent alignment disturbances while maintaining effective pretilt angle formation in other regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the potential parameter of the auxiliary capacitor line by applying multiple different potentials to different segments. This parameter modification allows optimization of the electric field distribution at critical intersection areas, preventing the formation of unwanted equipotential surfaces that cause alignment defects.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If auxiliary capacitor line is present, then pixel electrode potential is maintained, but equipotential surfaces cause alignment disturbances at intersections

Engineering Contradiction:
Improvepixel electrode potential stabilityVSAvoidalignment accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent creates local potential optimization by dividing the auxiliary capacitor line into multiple potential regions. This allows specific areas (intersections with pixel electrode slits) to have potentials that prevent equipotential surface formation, while other areas maintain the potential needed for pixel electrode stability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces a potential control mechanism that acts as an intermediary between the auxiliary capacitor line and the pixel electrode slits. By controlling the potential distribution along the auxiliary capacitor line, it mediates the interaction to prevent harmful equipotential surface formation while maintaining the necessary electrical connection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If metal layer is added to cover auxiliary capacitor line, then alignment disturbances are prevented, but device complexity increases

Engineering Contradiction:
Improvealignment accuracyVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent makes the auxiliary capacitor line serve multiple functions: it maintains pixel electrode potential stability while simultaneously having its potential distributed in a controlled manner to prevent alignment disturbances. This multi-functionality eliminates the need for separate metal layer structures, achieving alignment protection without increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the potential control function with the existing auxiliary capacitor line structure. Instead of adding a separate metal layer, the potential control is integrated into the auxiliary capacitor line itself, merging the alignment protection function with the existing electrical structure.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration ensures accurate pretilt angle formation and prevents alignment defects, resulting in improved display quality by maintaining proper liquid crystal alignment and reducing disturbances.

Implementation Method 1

block the influence of equipotential surfaces and maintain proper liquid crystal alignment

Methodology Applied
Scientific EffectEquipotential surfaces: Electrostatics

Implementation Method 2

maintain proper liquid crystal alignment during both manufacturing and operation

Methodology Applied
Scientific EffectElectrical field: Electric Field

Data Source

PatentUS8736779B2Active matrix substrate, liquid crystal display panel, liquid crystal display device, method for manufacturing active matrix substrate, method for manufacturing liquid crystal display panel, and method for driving liquid crystal display panel
Publication Date: 2014.05.27 SHARP KK
  • US8736779B2 patent drawing
  • US8736779B2 patent drawing
  • US8736779B2 patent drawing

AI summary

A high-quality display is achieved by suppressing a disturbance in alignment in a liquid crystal display panel including a substrate structured so that a slit in a pixel electrode intersects with a scanning signal line or an auxiliary capacitor line. An active matrix substrate (10) includes: a pixel electrode (12) having a slit; and an auxiliary capacitor line (14). In a region of intersection between the slit (15) and the auxiliary capacitor line (14) or a scanning signal line (21), at least a drain line (13) or a data signal line (22) is provided between a layer of the pixel electrode (12) and a layer of the auxiliary capacitor line (14) or of the scanning signal line (21) in such a way as to cover the auxiliary capacitor line (12) or the scanning signal line (21).