Auxiliary Capacitors in Dummy Sub-Pixels for GOA Noise Reduction
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Solution Overview
Problem
The existing Gate Driver on Array (GOA) circuits in display technology face challenges in reducing noise coupling due to the capacitance of the bootstrap capacitor, which increases the area occupied in the non-active region, hindering the narrow frame design and causing inconsistencies in the etching process across the active area.
Innovation Solution
The proposed solution involves extending gate lines and data lines to form dummy sub-pixels in the non-active area, incorporating auxiliary capacitors in these dummy sub-pixels to increase the capacitance of the bootstrap capacitor, thereby reducing noise coupling and allowing for a more consistent etching process while maintaining a narrow frame design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the capacitance of the bootstrap capacitor is increased to reduce noise coupling in GOA circuits, then noise coupling is reduced, but the area occupied in the non-active region increases
Solution Approach 1:
The patent divides the bootstrap capacitor into two separate capacitors: a first capacitor connected to the gate electrode and a second capacitor connected to the source electrode. This segmentation allows the total capacitance to be distributed across different locations, reducing noise coupling while avoiding concentration of large capacitance in one area of the non-active region.
Solution Approach 2:
The patent extends gate lines and data lines into the non-active area to form dummy sub-pixels, utilizing the spatial dimension of the non-active region to accommodate capacitor structures. This approach distributes the capacitance physically across extended line structures rather than concentrating it in a single location, thereby reducing noise coupling effects.
2Object-affected harmful factors
If gate lines and data lines are extended to form dummy sub-pixels in the non-active area, then noise coupling is reduced and etching uniformity is improved, but the device complexity increases
Solution Approach 1:
The extended gate lines and data lines serving as dummy sub-pixels perform multiple functions: they improve etching uniformity across the active area, provide additional capacitance for noise reduction, and maintain the narrow frame design. This multi-functionality justifies the extended structure by delivering multiple benefits from a single design modification.
Solution Approach 2:
The dummy sub-pixels created by extending gate and data lines have identical structures to actual sub-pixels, ensuring homogeneous etching conditions across the entire substrate. This structural homogeneity simplifies the manufacturing process by allowing uniform treatment of all pixel regions during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases noise coupling and ensures uniformity in the etching process, enhancing the operational efficiency of the display by maintaining a narrow frame design and consistent pixel patterns across the active area.
Implementation Method 1
incorporating auxiliary capacitors in these dummy sub-pixels to increase the capacitance of the bootstrap capacitor
Data Source
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AI summary
An array substrate may include a plurality of gate line (GL), a plurality of data lines (DL) intersecting the gate lines (GL), and a first gate driving circuit comprising a plurality of shift register circuits in a non-active area (11). The gate lines (GL) and the data lines (DL) may define a plurality of sub-pixels (22) in an active area (10) and a plurality of dummy sub-pixels (21) in the non-active area (11) adjacent to the active area (10). The first gate driving circuit (20) may be farther away from the active area (10) than the plurality of the dummy sub-pixels (21). At least one of the dummy sub-pixels (21) may include an auxiliary capacitor (40). A shift register circuit in the first gate driving circuit (20) may be coupled to the auxiliary capacitor (40). The auxiliary capacitor (40) may form at least a part of a bootstrap capacitor (Cst) in the shift register circuit.