Auxiliary CDR Circuit Switching for Wide-Range PAM4/NRZ Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock and data recovery (CDR) circuits in high-speed serial communications face challenges in maintaining accurate sampling clock phase, especially in the presence of jitter and noise, leading to long locking times and potential data loss, particularly when supporting new standards like PCIe 5.0 and PCIe 6.0 which require larger parts per million (ppm) acquisition and tracking.
Innovation Solution
An analog auxiliary clock and data recovery (CDR) path is implemented using a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL, enabling larger ppm acquisition and tracking, and supporting both PAM4 and NRZ signaling, with a programmable logic block configuration to support multiple data rates and flexible channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an edge-sampled CDR circuit oversamples the analog input waveform to generate the correct data sampling clock, then the sampling clock phase accuracy is improved, but the clocking power consumption increases
Solution Approach 1:
The patent implements a dynamic switching mechanism between two CDR paths (first CDR circuit for initial acquisition and second CDR circuit for tracking). The system transitions from oversampling mode to synchronized sampling mode based on operational stage, reducing power consumption while maintaining phase accuracy. The switching controller dynamically selects which CDR path is active based on lock status and operational requirements.
2Measurement precision
If the data sampling clock is maintained at the center between Zero-crossing points, then the sampling accuracy is improved for symmetric waveforms, but the performance degrades when the analog waveform becomes asymmetric due to channel loss changes
Solution Approach 1:
The system dynamically adjusts the sampling clock phase based on the operational mode. During initial acquisition, the first CDR circuit centers the clock between Zero-crossing points for symmetric waveforms. During tracking mode, the second CDR circuit adjusts the phase to optimize performance for asymmetric waveforms caused by channel loss, providing adaptability across different channel conditions.
Solution Approach 2:
The patent changes the sampling clock phase parameter dynamically based on the operational stage and channel conditions. The system transitions from a fixed center-aligned phase during acquisition to an adjustable phase during tracking, allowing optimization for asymmetric waveforms while maintaining simplicity during initial lock.
3Device complexity
If the CDR circuit operates far from the center of the data eye, then the initial setup is simpler, but the locking time increases leading to data loss
Solution Approach 1:
The CDR function is segmented into two distinct circuits: the first CDR circuit handles initial acquisition with a simplified structure that can quickly lock even when starting far from the center of the data eye, while the second CDR circuit handles precise tracking with optimized phase adjustment capabilities. This segmentation allows each circuit to be specialized for its specific function, reducing overall locking time.
Solution Approach 2:
The first CDR circuit performs preliminary acquisition by quickly establishing initial lock before the second CDR circuit takes over for precise tracking. This preliminary action gets the system into a functional state rapidly, after which the more sophisticated second CDR circuit refines the phase alignment, effectively reducing the overall locking time while maintaining simplicity in the initial acquisition phase.
Data Source
AI summary
Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.