Auxiliary Channel Structures for Etch Loading Uniformity in 3D Semiconductor Devices
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Solution Overview
Problem
In three-dimensional semiconductor devices, etch loading becomes non-uniform during the process of forming word line separation structures, leading to inconsistencies in channel hole formation, which affects the integration and reliability of semiconductor elements.
Innovation Solution
A semiconductor device design featuring a substrate with alternately stacked insulating layers and gate electrode layers, including first and second channel structures, a separation structure, and auxiliary channel structures that penetrate the mold structure, reducing the number of processes and ensuring uniformity in pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of layers of word lines and channel holes is increased to improve integration, then the degree of integration improves, but etch loading becomes non-uniform during etching process
Solution Approach 1:
The patent introduces auxiliary channel structures between the main channel holes to segment the etching process into multiple smaller openings. This segmentation distributes the etch loading more uniformly across the mold structure, preventing the non-uniformity that occurs when etching deep, narrow channel holes alone. The auxiliary channel structures act as additional etching pathways that balance the material removal across the entire structure.
Solution Approach 2:
The auxiliary channel structures serve as intermediary elements between the main channel holes and the mold structure. These intermediate structures facilitate more uniform etching by providing additional pathways for the etchant to reach the mold structure, thereby mediating the etch loading distribution and improving overall uniformity.
2Reliability
If traditional fabrication processes are used for forming patterns, then manufacturing reliability is maintained, but the number of processes is excessive and complex
Solution Approach 1:
The patent merges the formation of main channel holes and auxiliary channel structures into a single integrated fabrication process. By designing the pattern formation process to create both types of structures simultaneously using the same etching parameters and process steps, the total number of separate processes is reduced while maintaining the reliability achieved through proven fabrication techniques.
Solution Approach 2:
The fabrication process is designed to be universal, handling both main channel holes and auxiliary channel structures with the same process steps. This multi-functional approach allows a single etching process to perform multiple functions: creating main channels, creating auxiliary channels, and ensuring uniform etch loading distribution, thereby reducing process complexity without sacrificing reliability.
Data Source
AI summary
A semiconductor device includes a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate disposed on a peripheral circuit region and has a cell array region formed therein, a first mold structure which includes insulating layers and gate electrode layers alternately stacked on the substrate, first and second channel structures penetrating, in a third direction perpendicular to the first direction and the second direction, the first mold structure and spaced apart from each other in the first direction, a separation structure penetrating the first mold structure in the third direction between the first and second channel structures and separating the gate electrode layers in the first direction, and first and second auxiliary channel structures penetrating a part of the first mold structure between the separation structure and the first channel structure, and between the separation structure and the second channel structure.