Auxiliary Circuit Switching for Split-Lock Processor Coherency
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Solution Overview
Problem
In safety-critical data processing applications, existing split-lock processors face challenges in maintaining coherency across auxiliary circuits when switching from performance mode to safety mode, leading to performance penalties due to the need for complex coherency schemes and auxiliary circuit flushes.
Innovation Solution
A split-lock processor architecture where each processor has a locked mode for common operations and a split mode for different operations, utilizing a shared auxiliary circuit in safety mode to ensure consistent responses without duplicating non-safety-critical auxiliary circuits, thereby simplifying the circuit configuration and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If auxiliary circuits are flushed on entry to safety mode to achieve coherency, then coherency is achieved, but performance is significantly penalized
Solution Approach 1:
The system performs preliminary actions by switching the auxiliary circuit from the first processor to the second processor before the safety mode comparison begins. This preliminary switching ensures that both processors will access the same auxiliary circuit data during safety mode without requiring a full flush operation, thus maintaining performance while achieving coherency.
Solution Approach 2:
The auxiliary circuit is made dynamic by allowing it to be switched between different processors based on the operational mode. In performance mode, each processor can use its own auxiliary circuit for independent operation, while in safety mode, the auxiliary circuit is switched to be shared between processors, enabling coherency without static duplication.
2Reliability
If complex coherency schemes are implemented to ensure consistent responses from auxiliary circuits, then coherency is achieved, but device complexity increases
Solution Approach 1:
The system merges the auxiliary circuit resources by having both processors share the same auxiliary circuit during safety mode through switching. Instead of maintaining separate auxiliary circuits for each processor (which would increase complexity), the system combines their access to a single shared auxiliary circuit, reducing overall device complexity while ensuring coherency.
Solution Approach 2:
The auxiliary circuit is designed with universal access capability, allowing it to serve multiple processors depending on the operational mode. This multi-functionality enables the same auxiliary circuit to be used by either processor individually in performance mode or by both processors together in safety mode, eliminating the need for complex processor-specific auxiliary circuits.
Data Source
AI summary
A multiple-processor system 2 is provided where each processor 4-0, 4-1 can be dynamically switched between running in a locked mode where one processor 4-1 checks the operation of the other processor 4-0 and a split mode where each processor 4-0, 4-1 operates independently. Multiple auxiliary circuits 8-0, 8-1 provide auxiliary functions for the plurality of processors 4-0, 4-1. In the split mode, each auxiliary circuit 8-0, 8-1 separately provides auxiliary functions for a corresponding one of the processors 4-0, 4-1. To ensure coherency when each processor 4-0, 4-1 executes a common set of processing operations, in the locked mode a shared one of the auxiliary circuits 8-0 provides auxiliary functions for all of the processors 4-0, 4-1.