Auxiliary Clock Phase Alignment for Minimum Jitter Circuits

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Solution Overview

Problem

Current mixed signal circuitry, particularly in integrated circuits, experiences significant jitter due to non-zero transition times, which limits the accuracy and speed of signal processing, and existing methods to reduce jitter are not fully effective as data rates increase.

Innovation Solution

A clock and clock adjustment circuit that determines a low noise phase region of a primary clock and adjusts the phase of an auxiliary clock to fall within this region, minimizing jitter by aligning transitions with low noise periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If signal processing speed is increased, then productivity is improved, but jitter increases which worsens signal accuracy

Engineering Contradiction:

Improvesignal processing speedVSAvoidsignal accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent identifies low noise phase regions in advance and pre-adjusts the auxiliary clock phase to align transitions with these regions. By determining the low noise phase region beforehand and positioning the auxiliary clock transition accordingly, the system proactively minimizes jitter impact on signal accuracy while maintaining high processing speeds

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the phase parameter of the auxiliary clock to align its transitions with low noise regions of the primary clock. By adjusting the phase offset and positioning transitions during periods of minimal noise activity, the system reduces jitter while preserving high signal processing speed

Inventive Principle:

Principle #35Parameter changes

2Speed

If rise and fall times are decreased, then signal speed is improved, but jitter is not fully eliminated

Engineering Contradiction:

Improvesignal transition speedVSAvoidjitter reduction effectiveness

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent introduces an auxiliary clock as an intermediary signal to clock jitter-sensitive circuits. By using this intermediate clock signal with carefully controlled transitions aligned to low noise regions, the system achieves reliable jitter reduction while maintaining fast signal processing speeds

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If voltage stability is improved, then signal reliability is enhanced, but jitter is not completely eliminated

Engineering Contradiction:

Improvevoltage stabilityVSAvoidresidual jitter

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and addresses the jitter problem separately from voltage stability improvements. By identifying and isolating the clock transition timing as the source of jitter, the system applies targeted phase adjustment to eliminate residual jitter that remains despite voltage stability enhancements

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS8005181B1Clock and clock adjustment circuit for minimum jitter

Publication Date: 2011.08.23 XILINX INC

AI summary

A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noise phase region of the primary clock to produce an adjusted auxiliary clock.