Glitch-Free Clock Switching via Auxiliary Signal Mediator
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Solution Overview
Problem
Clock switch devices for system-on-chip (SoC) often produce glitches during mode switching, leading to incorrect operation of logic circuits due to imperfections in output clock signals.
Innovation Solution
A clock switch device with a controller and switching circuit that sets a clock switch period using a control signal, outputs one clock signal as glitch-free before and after the switch period, and uses an auxiliary clock signal during the switch period to prevent glitches, ensuring seamless mode transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock switch device switches between high speed mode and low speed mode using conventional methods, then mode switching is achieved, but glitches are generated in the output clock signal during switching
Solution Approach 1:
The patent introduces an auxiliary clock signal as an intermediary during the transition between high speed mode and low speed mode. This auxiliary clock signal serves as a mediator that prevents direct switching between the two clock signals, thereby eliminating glitches in the output clock signal while maintaining reliable mode switching capability.
2Adaptability or versatility
If a conventional clock switch device is used for mode switching, then switching between operating modes is achieved, but logic circuits may operate incorrectly due to glitches
Solution Approach 1:
The auxiliary clock signal acts as a protective intermediary during mode transitions, preventing the generation of glitches that would otherwise cause logic circuit errors. This intermediary approach maintains operating mode flexibility while eliminating harmful glitch effects on logic circuits.
3Speed
If direct switching between clock signals is performed, then mode transition speed is improved, but signal integrity deteriorates due to glitch generation
Solution Approach 1:
The auxiliary clock signal provides a smooth transition pathway between high speed and low speed modes, maintaining signal integrity during switching. This intermediary approach enables fast mode transitions without sacrificing clock signal integrity, as the auxiliary clock bridges the transition without generating glitches.
Data Source
AI summary
A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.